RTNETLINK answers: File exists synthesis -f "Project_impl1_lattice.synproj" synthesis: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Thu Aug 15 09:57:03 2024 Command Line: synthesis -f Project_impl1_lattice.synproj INFO - synthesis: Lattice Synthesis Engine Launched. Synthesis options: The -a option is MachXO2. The -s option is 4. The -t option is TQFP144. The -d option is LCMXO2-7000HC. Using package TQFP144. Using performance grade 4. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-7000HC ### Package : TQFP144 ### Speed : 4 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = TOP_LEVEL. Target frequency = 54.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /usr/local/diamond/3.12/ispfpga/xo2c00/data (searchpath added) -p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/build (searchpath added) -p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga (searchpath added) VHDL library = work VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_CROSSBAR_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_MODULE_CONFIG.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_CROSSBAR_CONFIG.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/GPIO_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/PWM_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/LED_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/IO_CROSSBAR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_TABLE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_UNIT.vhd NGD file = Project_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. -vh2008 Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file /usr/local/diamond/3.12/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin INFO - synthesis: The default VHDL library search path is now "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/build". VHDL-1504 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(39): analyzing package goldi_comm_standard. VHDL-1014 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(255): analyzing package body goldi_comm_standard. VHDL-1013 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd(32): analyzing package goldi_io_standard. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_CROSSBAR_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_CROSSBAR_STANDARD.vhd(40): analyzing package goldi_crossbar_standard. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_MODULE_CONFIG.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_MODULE_CONFIG.vhd(33): analyzing package goldi_module_config. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_CROSSBAR_CONFIG.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_CROSSBAR_CONFIG.vhd(42): analyzing package goldi_crossbar_config. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER.vhd(38): analyzing entity synchronizer. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER.vhd(54): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(47): analyzing entity sp_converter. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(71): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(75): analyzing entity bus_adaptor. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(96): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(77): analyzing entity goldi_spi_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(97): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_UNIT.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_UNIT.vhd(63): analyzing entity register_unit. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_UNIT.vhd(87): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER.vhd(42): analyzing entity tris_buffer. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER.vhd(60): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(42): analyzing entity tris_buffer_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(63): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_TABLE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_TABLE.vhd(82): analyzing entity register_table. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_TABLE.vhd(107): analyzing architecture bh. VHDL-1010 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_TABLE.vhd(196): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/GPIO_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/GPIO_SMODULE.vhd(60): analyzing entity gpio_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/GPIO_SMODULE.vhd(82): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/PWM_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/PWM_SMODULE.vhd(49): analyzing entity pwm_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/PWM_SMODULE.vhd(71): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/LED_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/LED_SMODULE.vhd(71): analyzing entity led_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/LED_SMODULE.vhd(93): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/IO_CROSSBAR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/IO_CROSSBAR.vhd(79): analyzing entity io_crossbar. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/IO_CROSSBAR.vhd(106): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd(49): analyzing entity top_level. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd(69): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd(38): analyzing entity synchronizer_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd(55): analyzing architecture rtl. VHDL-1010 unit TOP_LEVEL is not yet analyzed. VHDL-1485 /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd(49): executing TOP_LEVEL(RTL) WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd(63): replacing existing netlist TOP_LEVEL(RTL). VHDL-1205 Top module name (VHDL): TOP_LEVEL Last elaborated design is TOP_LEVEL(RTL) Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Top-level module name = TOP_LEVEL. INFO - synthesis: Extracted state machine for register '\SPI_BUS_COMMUNICATION/BUS_INTERFACE/ps_mbus' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 WARNING - synthesis: Skipping pad insertion on IO_DATA[65] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[64] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[63] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[62] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[61] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[60] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[59] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[58] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[57] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[56] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[55] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[54] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[53] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[52] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[51] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[50] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[49] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[48] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[47] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[46] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[45] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[44] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[43] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[42] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[41] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[40] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[39] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[38] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[37] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[36] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[35] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[34] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[33] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[32] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[31] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[30] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[29] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[28] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[27] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[26] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[25] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[24] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[23] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[22] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[21] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[20] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[19] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[18] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[17] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[16] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[15] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[14] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[13] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[12] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[11] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[10] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[9] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[8] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[7] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[6] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[5] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[4] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[3] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[2] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[1] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[0] due to black_box_pad_pin attribute. GSR instance connected to net n9622. Applying 54.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in TOP_LEVEL_drc.log. Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Running DRC... WARNING - synthesis: logical net 'port_in_async_64_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_65_.dat' has no load. WARNING - synthesis: DRC complete with 2 warnings. Design Results: 6565 blocks expanded completed the first expansion All blocks are expanded and NGD expansion is successful. Writing NGD file Project_impl1.ngd. ################### Begin Area Report (TOP_LEVEL)###################### Number of register bits => 2301 of 7209 (31 % ) BB => 66 CCU2D => 254 FD1P3AX => 1190 FD1P3AY => 194 FD1P3IX => 162 FD1P3JX => 16 FD1S3AX => 194 FD1S3AY => 17 FD1S3IX => 526 FD1S3JX => 2 GSR => 1 IB => 5 L6MUX21 => 373 LUT4 => 2829 OB => 1 PFUMX => 732 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : ClockFPGA_c, loads : 2301 Clock Enable Nets Number of Clock Enables: 271 Top 10 highest fanout Clock Enables: Net : SPI_BUS_COMMUNICATION/BUS_INTERFACE/ClockFPGA_c_enable_1378, loads : 10 Net : PWM_SIGNALS_9..PWM_DRIVER/ClockFPGA_c_enable_472, loads : 9 Net : PWM_SIGNALS_15..PWM_DRIVER/ClockFPGA_c_enable_430, loads : 9 Net : PWM_SIGNALS_14..PWM_DRIVER/ClockFPGA_c_enable_437, loads : 9 Net : PWM_SIGNALS_10..PWM_DRIVER/MEMORY/p_data_out_7__N_2439, loads : 9 Net : PWM_SIGNALS_14..PWM_DRIVER/MEMORY/p_data_out_7__N_2771, loads : 9 Net : PWM_SIGNALS_12..PWM_DRIVER/ClockFPGA_c_enable_451, loads : 9 Net : PWM_SIGNALS_8..PWM_DRIVER/ClockFPGA_c_enable_479, loads : 9 Net : PWM_SIGNALS_0..PWM_DRIVER/MEMORY/p_data_out_7__N_1609, loads : 9 Net : PWM_SIGNALS_7..PWM_DRIVER/ClockFPGA_c_enable_486, loads : 9 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : SPI_BUS_COMMUNICATION/BUS_INTERFACE/master_bus_o.adr_0, loads : 507 Net : n27491, loads : 258 Net : n27468, loads : 146 Net : sys_bus_i.dat_7, loads : 82 Net : sys_bus_i.dat_6, loads : 82 Net : sys_bus_i.dat_5, loads : 82 Net : sys_bus_i.dat_4, loads : 82 Net : sys_bus_i.dat_3, loads : 82 Net : sys_bus_i.dat_2, loads : 82 Net : sys_bus_i.dat_1, loads : 82 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 18.518519 -name | | | clk0 [get_nets ClockFPGA_c] | 54.001 MHz| 56.702 MHz| 11 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 284.887 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 9.236 secs -------------------------------------------------------------- Nothing is executed for the "Translate" process map -a "MachXO2" -p LCMXO2-7000HC -t TQFP144 -s 4 -oc Commercial "Project_impl1.ngd" -o "Project_impl1_map.ncd" -pr "Project_impl1.prf" -mp "Project_impl1.mrp" -lpf "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/build/Project_impl1.lpf" -lpf "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/constraints.lpf" -c 0 map: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Process the file: Project_impl1.ngd Picdevice="LCMXO2-7000HC" Pictype="TQFP144" Picspeed=4 Remove unused logic Do not produce over sized NCDs. Part used: LCMXO2-7000HCTQFP144, Performance used: 4. Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Running general design DRC... Removing unused logic... Optimizing... Design Summary: Number of registers: 2301 out of 7209 (32%) PFU registers: 2301 out of 6864 (34%) PIO registers: 0 out of 345 (0%) Number of SLICEs: 1943 out of 3432 (57%) SLICEs as Logic/ROM: 1943 out of 3432 (57%) SLICEs as RAM: 0 out of 2574 (0%) SLICEs as Carry: 254 out of 3432 (7%) Number of LUT4s: 3336 out of 6864 (49%) Number used as logic LUTs: 2828 Number used as distributed RAM: 0 Number used as ripple logic: 508 Number used as shift registers: 0 Number of PIO sites used: 72 + 4(JTAG) out of 115 (66%) Number of block RAMs: 0 out of 26 (0%) Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 2 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 1 Net ClockFPGA_c: 1309 loads, 1309 rising, 0 falling (Driver: PIO ClockFPGA ) Number of Clock Enables: 271 Net ClockFPGA_c_enable_654: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_626: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_615: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_1385: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_613: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_605: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_607: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_122: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_545: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_537: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_300: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_307: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_754: 8 loads, 8 LSLICEs Net ClockFPGA_c_enable_611: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_619: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_543: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_539: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_541: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_328: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_335: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_777: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_891: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_884: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_856: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_843: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_847: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_839: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_837: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_349: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_345: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_726: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_712: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_705: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_698: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_547: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_337: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_413: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_109: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_110: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_277: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_111: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_107: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_411: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_420: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_416: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_113: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_849: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_589: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_582: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_554: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_407: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_400: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_418: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_372: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_907: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_1383: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_8/ClockFPGA_c_enable_835: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_8/ClockFPGA_c_enable_841: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_8/ClockFPGA_c_enable_845: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_8/ClockFPGA_c_enable_863: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_870: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_877: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_898: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_905: 8 loads, 8 LSLICEs Net ClockFPGA_c_enable_118: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_114: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_409: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_112: 2 loads, 2 LSLICEs Net p_data_out_7__N_269: 6 loads, 6 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/ClockFPGA_c_enable_535: 4 loads, 4 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/ClockFPGA_c_enable_762: 1 loads, 1 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/MEMORY/p_data_out_7__N_1609: 4 loads, 4 LSLICEs Net PWM_SIGNALS_10..PWM_DRIVER/ClockFPGA_c_enable_198: 1 loads, 1 LSLICEs Net PWM_SIGNALS_10..PWM_DRIVER/ClockFPGA_c_enable_465: 4 loads, 4 LSLICEs Net PWM_SIGNALS_10..PWM_DRIVER/MEMORY/p_data_out_7__N_2439: 4 loads, 4 LSLICEs Net p_data_out_7__N_2688: 4 loads, 4 LSLICEs Net p_data_out_7__N_2605: 4 loads, 4 LSLICEs Net p_data_out_7__N_2522: 4 loads, 4 LSLICEs Net PWM_SIGNALS_11..PWM_DRIVER/ClockFPGA_c_enable_196: 1 loads, 1 LSLICEs Net PWM_SIGNALS_11..PWM_DRIVER/ClockFPGA_c_enable_458: 4 loads, 4 LSLICEs Net PWM_SIGNALS_12..PWM_DRIVER/ClockFPGA_c_enable_178: 1 loads, 1 LSLICEs Net PWM_SIGNALS_12..PWM_DRIVER/ClockFPGA_c_enable_451: 4 loads, 4 LSLICEs Net PWM_SIGNALS_13..PWM_DRIVER/ClockFPGA_c_enable_177: 1 loads, 1 LSLICEs Net PWM_SIGNALS_13..PWM_DRIVER/ClockFPGA_c_enable_444: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_733: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_916: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_923: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_930: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_937: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_944: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_951: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_958: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_965: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_972: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_979: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_986: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_993: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1000: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1007: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1014: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1021: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1028: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1035: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1042: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1049: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1056: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1063: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1070: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1077: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_1084: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1091: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1098: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1105: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1112: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1119: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1126: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1133: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_1140: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1147: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1154: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1161: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1168: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1175: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1182: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1189: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1196: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1203: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1210: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1217: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1224: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1231: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1238: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1245: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1252: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1259: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1266: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1273: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1280: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1287: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1294: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1301: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_1308: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1315: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1322: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1329: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1336: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1343: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1350: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1357: 4 loads, 4 LSLICEs Net p_data_out_7__N_1858: 4 loads, 4 LSLICEs Net PWM_SIGNALS_9..PWM_DRIVER/ClockFPGA_c_enable_472: 4 loads, 4 LSLICEs Net PWM_SIGNALS_9..PWM_DRIVER/ClockFPGA_c_enable_1387: 1 loads, 1 LSLICEs Net p_data_out_7__N_2356: 4 loads, 4 LSLICEs Net PWM_SIGNALS_15..PWM_DRIVER/ClockFPGA_c_enable_159: 1 loads, 1 LSLICEs Net PWM_SIGNALS_15..PWM_DRIVER/ClockFPGA_c_enable_430: 4 loads, 4 LSLICEs Net p_data_out_7__N_2854: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_286: 8 loads, 8 LSLICEs Net ClockFPGA_c_enable_314: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_293: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_321: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_279: 2 loads, 2 LSLICEs Net POWER_RED/blink_counter_enb: 4 loads, 4 LSLICEs Net p_data_out_7__N_2956: 4 loads, 4 LSLICEs Net PWM_SIGNALS_14..PWM_DRIVER/ClockFPGA_c_enable_175: 1 loads, 1 LSLICEs Net PWM_SIGNALS_14..PWM_DRIVER/ClockFPGA_c_enable_437: 4 loads, 4 LSLICEs Net PWM_SIGNALS_14..PWM_DRIVER/MEMORY/p_data_out_7__N_2771: 4 loads, 4 LSLICEs Net p_data_out_7__N_3058: 4 loads, 4 LSLICEs Net PWM_SIGNALS_8..PWM_DRIVER/ClockFPGA_c_enable_479: 4 loads, 4 LSLICEs Net PWM_SIGNALS_8..PWM_DRIVER/ClockFPGA_c_enable_1388: 1 loads, 1 LSLICEs Net p_data_out_7__N_2273: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_379: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_108: 2 loads, 2 LSLICEs Net PWM_SIGNALS_7..PWM_DRIVER/ClockFPGA_c_enable_486: 4 loads, 4 LSLICEs Net PWM_SIGNALS_7..PWM_DRIVER/ClockFPGA_c_enable_1389: 1 loads, 1 LSLICEs Net p_data_out_7__N_2190: 4 loads, 4 LSLICEs Net PWM_SIGNALS_6..PWM_DRIVER/ClockFPGA_c_enable_493: 4 loads, 4 LSLICEs Net PWM_SIGNALS_6..PWM_DRIVER/ClockFPGA_c_enable_1390: 1 loads, 1 LSLICEs Net PWM_SIGNALS_6..PWM_DRIVER/MEMORY/p_data_out_7__N_2107: 4 loads, 4 LSLICEs Net PWM_SIGNALS_5..PWM_DRIVER/ClockFPGA_c_enable_500: 4 loads, 4 LSLICEs Net PWM_SIGNALS_5..PWM_DRIVER/ClockFPGA_c_enable_1391: 1 loads, 1 LSLICEs Net p_data_out_7__N_2024: 4 loads, 4 LSLICEs Net PWM_SIGNALS_4..PWM_DRIVER/ClockFPGA_c_enable_507: 4 loads, 4 LSLICEs Net PWM_SIGNALS_4..PWM_DRIVER/ClockFPGA_c_enable_1392: 1 loads, 1 LSLICEs Net p_data_out_7__N_1941: 4 loads, 4 LSLICEs Net PWM_SIGNALS_3..PWM_DRIVER/ClockFPGA_c_enable_514: 4 loads, 4 LSLICEs Net PWM_SIGNALS_3..PWM_DRIVER/ClockFPGA_c_enable_1393: 1 loads, 1 LSLICEs Net PWM_SIGNALS_2..PWM_DRIVER/ClockFPGA_c_enable_521: 4 loads, 4 LSLICEs Net PWM_SIGNALS_2..PWM_DRIVER/ClockFPGA_c_enable_760: 1 loads, 1 LSLICEs Net PWM_SIGNALS_2..PWM_DRIVER/MEMORY/p_data_out_7__N_1775: 4 loads, 4 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/ClockFPGA_c_enable_528: 4 loads, 4 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/ClockFPGA_c_enable_761: 1 loads, 1 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/MEMORY/p_data_out_7__N_1692: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_609: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_617: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_633: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_640: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_647: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_661: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_668: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_675: 8 loads, 8 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_423: 3 loads, 3 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_32: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_765: 3 loads, 3 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_686: 4 loads, 4 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_909: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_1394: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_1381: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_1382: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_1384: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_1386: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_1379: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_1380: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_194: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1361: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1358: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1359: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1360: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1362: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1363: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1364: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1365: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1366: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1367: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_1368: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/BUS_INTERFACE/ClockFPGA_c_enable_1378: 5 loads, 5 LSLICEs Net POWER_GREEN/blink_counter_enb: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_121: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_561: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_568: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_575: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_596: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_603: 8 loads, 8 LSLICEs Net IO_ROUTING_BANK_3/ClockFPGA_c_enable_120: 8 loads, 8 LSLICEs Net IO_ROUTING_BANK_3/ClockFPGA_c_enable_119: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_3/ClockFPGA_c_enable_117: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_3/ClockFPGA_c_enable_116: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_3/ClockFPGA_c_enable_115: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_747: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_677: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_679: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_688: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_690: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_692: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_694: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_696: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_719: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_740: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_393: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_386: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_365: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_358: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_819: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_791: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_784: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_812: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_771: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_773: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_767: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_775: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_758: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_756: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_769: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_798: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_805: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_826: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_833: 8 loads, 8 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_351: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_347: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_343: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_341: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_339: 2 loads, 2 LSLICEs Number of LSRs: 67 Net n27583: 13 loads, 13 LSLICEs Net n9650: 8 loads, 8 LSLICEs Net n9643: 8 loads, 8 LSLICEs Net n9642: 8 loads, 8 LSLICEs Net n9645: 8 loads, 8 LSLICEs Net n27355: 8 loads, 8 LSLICEs Net n9640: 8 loads, 8 LSLICEs Net n9644: 8 loads, 8 LSLICEs Net n9641: 8 loads, 8 LSLICEs Net n27358: 4 loads, 4 LSLICEs Net n9671: 8 loads, 8 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/n3376: 9 loads, 9 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/n3379: 5 loads, 5 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/MEMORY/n27385: 4 loads, 4 LSLICEs Net PWM_SIGNALS_10..PWM_DRIVER/n3449: 5 loads, 5 LSLICEs Net PWM_SIGNALS_10..PWM_DRIVER/n3446: 9 loads, 9 LSLICEs Net PWM_SIGNALS_10..PWM_DRIVER/MEMORY/n27370: 4 loads, 4 LSLICEs Net n27367: 4 loads, 4 LSLICEs Net n27368: 4 loads, 4 LSLICEs Net n27369: 4 loads, 4 LSLICEs Net PWM_SIGNALS_11..PWM_DRIVER/n3456: 5 loads, 5 LSLICEs Net PWM_SIGNALS_11..PWM_DRIVER/n3453: 9 loads, 9 LSLICEs Net PWM_SIGNALS_12..PWM_DRIVER/n3463: 5 loads, 5 LSLICEs Net PWM_SIGNALS_12..PWM_DRIVER/n3460: 9 loads, 9 LSLICEs Net PWM_SIGNALS_13..PWM_DRIVER/n3470: 5 loads, 5 LSLICEs Net PWM_SIGNALS_13..PWM_DRIVER/n3467: 9 loads, 9 LSLICEs Net n27377: 4 loads, 4 LSLICEs Net PWM_SIGNALS_9..PWM_DRIVER/n3439: 9 loads, 9 LSLICEs Net PWM_SIGNALS_9..PWM_DRIVER/n3442: 5 loads, 5 LSLICEs Net n27371: 4 loads, 4 LSLICEs Net PWM_SIGNALS_15..PWM_DRIVER/n3484: 5 loads, 5 LSLICEs Net PWM_SIGNALS_15..PWM_DRIVER/n3481: 9 loads, 9 LSLICEs Net n27365: 4 loads, 4 LSLICEs Net POWER_RED/led_counter_21__N_2918: 12 loads, 12 LSLICEs Net n27364: 4 loads, 4 LSLICEs Net PWM_SIGNALS_14..PWM_DRIVER/n3477: 5 loads, 5 LSLICEs Net PWM_SIGNALS_14..PWM_DRIVER/n3474: 9 loads, 9 LSLICEs Net PWM_SIGNALS_14..PWM_DRIVER/MEMORY/n27366: 4 loads, 4 LSLICEs Net n27363: 4 loads, 4 LSLICEs Net PWM_SIGNALS_8..PWM_DRIVER/n3432: 9 loads, 9 LSLICEs Net PWM_SIGNALS_8..PWM_DRIVER/n3435: 5 loads, 5 LSLICEs Net n27372: 4 loads, 4 LSLICEs Net PWM_SIGNALS_7..PWM_DRIVER/n3425: 9 loads, 9 LSLICEs Net PWM_SIGNALS_7..PWM_DRIVER/n3428: 5 loads, 5 LSLICEs Net n27373: 4 loads, 4 LSLICEs Net PWM_SIGNALS_6..PWM_DRIVER/n3418: 9 loads, 9 LSLICEs Net PWM_SIGNALS_6..PWM_DRIVER/n3421: 5 loads, 5 LSLICEs Net PWM_SIGNALS_6..PWM_DRIVER/MEMORY/n27374: 4 loads, 4 LSLICEs Net PWM_SIGNALS_5..PWM_DRIVER/n3411: 9 loads, 9 LSLICEs Net PWM_SIGNALS_5..PWM_DRIVER/n3414: 5 loads, 5 LSLICEs Net n27375: 4 loads, 4 LSLICEs Net PWM_SIGNALS_4..PWM_DRIVER/n3404: 9 loads, 9 LSLICEs Net PWM_SIGNALS_4..PWM_DRIVER/n3407: 5 loads, 5 LSLICEs Net n27376: 4 loads, 4 LSLICEs Net PWM_SIGNALS_3..PWM_DRIVER/n3400: 5 loads, 5 LSLICEs Net PWM_SIGNALS_3..PWM_DRIVER/n3397: 9 loads, 9 LSLICEs Net PWM_SIGNALS_2..PWM_DRIVER/n3390: 9 loads, 9 LSLICEs Net PWM_SIGNALS_2..PWM_DRIVER/n3393: 5 loads, 5 LSLICEs Net PWM_SIGNALS_2..PWM_DRIVER/MEMORY/n27381: 4 loads, 4 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/n3383: 9 loads, 9 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/n3386: 5 loads, 5 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/MEMORY/n27387: 4 loads, 4 LSLICEs Net SPI_BUS_COMMUNICATION/n6815: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/n27607: 16 loads, 16 LSLICEs Net SPI_BUS_COMMUNICATION/n6810: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/p_master_bus_o.adr_9__N_230: 10 loads, 10 LSLICEs Net POWER_GREEN/led_counter_21__N_3020: 12 loads, 12 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net master_bus_o.adr_0: 509 loads Net n27491: 258 loads Net n27468: 146 loads Net sys_bus_i.dat_0: 82 loads Net sys_bus_i.dat_1: 82 loads Net sys_bus_i.dat_2: 82 loads Net sys_bus_i.dat_3: 82 loads Net sys_bus_i.dat_4: 82 loads Net sys_bus_i.dat_5: 82 loads Net sys_bus_i.dat_6: 82 loads Number of warnings: 0 Number of errors: 0 Total CPU Time: 4 secs Total REAL Time: 4 secs Peak Memory Usage: 216 MB Dumping design to file Project_impl1_map.ncd. ncd2vdb "Project_impl1_map.ncd" ".vdbs/Project_impl1_map.vdb" Loading device for application ncd2vdb from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. mpartrce -p "Project_impl1.p2t" -f "Project_impl1.p3t" -tf "Project_impl1.pt" "Project_impl1_map.ncd" "Project_impl1.ncd" ---- MParTrce Tool ---- Removing old design directory at request of -rem command line option to this program. Running par. Please wait . . . Lattice Place and Route Report for Design "Project_impl1_map.ncd" Thu Aug 15 09:57:18 2024 PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 Project_impl1_map.ncd Project_impl1.dir/5_1.ncd Project_impl1.prf Preference file: Project_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file Project_impl1_map.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 72+4(JTAG)/336 23% used 72+4(JTAG)/115 66% bonded SLICE 1943/3432 56% used GSR 1/1 100% used Number of Signals: 5496 Number of Connections: 17401 Pin Constraint Summary: 72 out of 72 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: ClockFPGA_c (driver: ClockFPGA, clk load #: 1309) The following 5 signals are selected to use the secondary clock routing resources: SPI_BUS_COMMUNICATION/n27607 (driver: SLICE_890, clk load #: 0, sr load #: 16, ce load #: 0) n27583 (driver: SLICE_2548, clk load #: 0, sr load #: 13, ce load #: 0) POWER_RED/led_counter_21__N_2918 (driver: SLICE_460, clk load #: 0, sr load #: 12, ce load #: 0) POWER_GREEN/led_counter_21__N_3020 (driver: SLICE_451, clk load #: 0, sr load #: 12, ce load #: 0) SPI_BUS_COMMUNICATION/p_master_bus_o.adr_9__N_230 (driver: SLICE_577, clk load #: 0, sr load #: 10, ce load #: 0) Signal RESET_SYNC/FPGA_nReset_sync is selected as Global Set/Reset. Starting Placer Phase 0. .......... Finished Placer Phase 0. REAL time: 3 secs Starting Placer Phase 1. ....................... Placer score = 1530072. Finished Placer Phase 1. REAL time: 15 secs Starting Placer Phase 2. . Placer score = 1518478 Finished Placer Phase 2. REAL time: 17 secs ------------------ Clock Report ------------------ Global Clock Resources: CLK_PIN : 1 out of 8 (12%) PLL : 0 out of 2 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: PRIMARY "ClockFPGA_c" from comp "ClockFPGA" on CLK_PIN site "128 (PT18A)", clk load = 1309 SECONDARY "SPI_BUS_COMMUNICATION/n27607" from F1 on comp "SLICE_890" on site "R14C18C", clk load = 0, ce load = 0, sr load = 16 SECONDARY "n27583" from F0 on comp "SLICE_2548" on site "R14C18A", clk load = 0, ce load = 0, sr load = 13 SECONDARY "POWER_RED/led_counter_21__N_2918" from F0 on comp "SLICE_460" on site "R14C20B", clk load = 0, ce load = 0, sr load = 12 SECONDARY "POWER_GREEN/led_counter_21__N_3020" from F0 on comp "SLICE_451" on site "R21C20C", clk load = 0, ce load = 0, sr load = 12 SECONDARY "SPI_BUS_COMMUNICATION/p_master_bus_o.adr_9__N_230" from Q0 on comp "SLICE_577" on site "R14C18D", clk load = 0, ce load = 0, sr load = 10 PRIMARY : 1 out of 8 (12%) SECONDARY: 5 out of 8 (62%) Edge Clocks: No edge clock selected. --------------- End of Clock Report --------------- I/O Usage Summary (final): 72 + 4(JTAG) out of 336 (22.6%) PIO sites used. 72 + 4(JTAG) out of 115 (66.1%) bonded PIO sites used. Number of PIO comps: 72; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ | 0 | 3 / 28 ( 10%) | 3.3V | - | | 1 | 24 / 29 ( 82%) | 3.3V | - | | 2 | 21 / 29 ( 72%) | 3.3V | - | | 3 | 9 / 9 (100%) | 3.3V | - | | 4 | 10 / 10 (100%) | 3.3V | - | | 5 | 5 / 10 ( 50%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 17 secs Dumping design to file Project_impl1.dir/5_1.ncd. 0 connections routed; 17401 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 20 secs Start NBR router at Thu Aug 15 09:57:38 UTC 2024 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at Thu Aug 15 09:57:38 UTC 2024 Start NBR section for initial routing at Thu Aug 15 09:57:38 UTC 2024 Level 1, iteration 1 0(0.00%) conflict; 14351(82.47%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 20 secs Level 2, iteration 1 4(0.00%) conflicts; 14329(82.35%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 2.931ns/0.000ns; real time: 21 secs Level 3, iteration 1 7(0.00%) conflicts; 13706(78.77%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 3.267ns/0.000ns; real time: 22 secs Level 4, iteration 1 1162(0.31%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 3.151ns/0.000ns; real time: 25 secs Info: Initial congestion level at 75% usage is 11 Info: Initial congestion area at 75% usage is 175 (17.50%) Start NBR section for normal routing at Thu Aug 15 09:57:43 UTC 2024 Level 4, iteration 1 322(0.09%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.730ns/0.000ns; real time: 39 secs Level 4, iteration 2 147(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.113ns/0.000ns; real time: 43 secs Level 4, iteration 3 78(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.642ns/0.000ns; real time: 46 secs Level 4, iteration 4 66(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.642ns/0.000ns; real time: 47 secs Level 4, iteration 5 46(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.304ns/0.000ns; real time: 49 secs Level 4, iteration 6 34(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.304ns/0.000ns; real time: 49 secs Level 4, iteration 7 21(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.406ns/0.000ns; real time: 50 secs Level 4, iteration 8 11(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.406ns/0.000ns; real time: 51 secs Level 4, iteration 9 9(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.400ns/0.000ns; real time: 51 secs Level 4, iteration 10 9(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.400ns/0.000ns; real time: 52 secs Level 4, iteration 11 8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.406ns/0.000ns; real time: 53 secs Level 4, iteration 12 8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.406ns/0.000ns; real time: 54 secs Level 4, iteration 13 5(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.406ns/0.000ns; real time: 54 secs Level 4, iteration 14 7(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.406ns/0.000ns; real time: 55 secs Level 4, iteration 15 4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.406ns/0.000ns; real time: 56 secs Level 4, iteration 16 7(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.406ns/0.000ns; real time: 56 secs Level 4, iteration 17 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.406ns/0.000ns; real time: 57 secs Level 4, iteration 18 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.406ns/0.000ns; real time: 57 secs Level 4, iteration 19 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.082ns/0.000ns; real time: 57 secs Start NBR section for setup/hold timing optimization with effort level 3 at Thu Aug 15 09:58:15 UTC 2024 Start NBR section for re-routing at Thu Aug 15 09:58:16 UTC 2024 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.082ns/0.000ns; real time: 58 secs Start NBR section for post-routing at Thu Aug 15 09:58:16 UTC 2024 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack : 1.082ns Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 1 mins Total REAL time: 1 mins Completely routed. End of route. 17401 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file Project_impl1.dir/5_1.ncd. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack> = 1.082 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Worst slack> = 0.304 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 1 mins 1 secs Total REAL time to completion: 1 mins 1 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Exiting par with exit code 0 Exiting mpartrce with exit code 0 trce -f "Project_impl1.pt" -o "Project_impl1.twr" "Project_impl1.ncd" "Project_impl1.prf" trce: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application trce from file Project_impl1.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 Thu Aug 15 09:58:21 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Project_impl1.twr Project_impl1.ncd Project_impl1.prf Design file: Project_impl1.ncd Preference file: Project_impl1.prf Device,speed: LCMXO2-7000HC,4 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 59844 paths, 1 nets, and 14252 connections (81.90% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 Thu Aug 15 09:58:21 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Project_impl1.twr Project_impl1.ncd Project_impl1.prf Design file: Project_impl1.ncd Preference file: Project_impl1.prf Device,speed: LCMXO2-7000HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 59844 paths, 1 nets, and 14252 connections (81.90% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Total CPU Time: 1 secs Total REAL Time: 0 secs Peak Memory Usage: 180 MB Nothing is executed for the "PAR - PARTrace" process tmcheck -par "Project_impl1.par" bitgen -f "Project_impl1.t2b" -w "Project_impl1.ncd" "Project_impl1.prf" BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application Bitgen from file Project_impl1.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Running DRC. DRC detected 0 errors and 0 warnings. Reading Preference File from Project_impl1.prf. Preference Summary: +---------------------------------+---------------------------------+ | Preference | Current Setting | +---------------------------------+---------------------------------+ | RamCfg | Reset** | +---------------------------------+---------------------------------+ | MCCLK_FREQ | 2.08** | +---------------------------------+---------------------------------+ | CONFIG_SECURE | OFF** | +---------------------------------+---------------------------------+ | INBUF | ON** | +---------------------------------+---------------------------------+ | JTAG_PORT | ENABLE** | +---------------------------------+---------------------------------+ | SDM_PORT | DISABLE** | +---------------------------------+---------------------------------+ | SLAVE_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MASTER_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | I2C_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MUX_CONFIGURATION_PORTS | DISABLE** | +---------------------------------+---------------------------------+ | CONFIGURATION | CFG** | +---------------------------------+---------------------------------+ | COMPRESS_CONFIG | ON** | +---------------------------------+---------------------------------+ | MY_ASSP | OFF** | +---------------------------------+---------------------------------+ | ONE_TIME_PROGRAM | OFF** | +---------------------------------+---------------------------------+ | ENABLE_TRANSFR | DISABLE** | +---------------------------------+---------------------------------+ | SHAREDEBRINIT | DISABLE** | +---------------------------------+---------------------------------+ | BACKGROUND_RECONFIG | OFF** | +---------------------------------+---------------------------------+ * Default setting. ** The specified setting matches the default setting. Creating bit map... Bitstream Status: Final Version 1.95. Saving bit stream in "Project_impl1.bit". Total CPU Time: 3 secs Total REAL Time: 4 secs Peak Memory Usage: 440 MB RTNETLINK answers: File exists Lattice Diamond Deployment Tool 3.12 Command Line Loading Programmer Device Database... Generating SVF..... Reading Input File: build/Project_impl1.bit Output File: dist/bitstream.svf Generate Single SVF file: Start Device 1 LCMXO2-7000HC:SRAM Erase,Program,Verify Build SVF File Operation: Successful. Lattice Diamond Deployment Tool has exited successfully.