RTNETLINK answers: File exists synthesis -f "Project_impl1_lattice.synproj" synthesis: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Wed Sep 24 14:18:49 2025 Command Line: synthesis -f Project_impl1_lattice.synproj INFO - synthesis: Lattice Synthesis Engine Launched. Synthesis options: The -a option is MachXO2. The -s option is 4. The -t option is TQFP144. The -d option is LCMXO2-7000HC. Using package TQFP144. Using performance grade 4. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-7000HC ### Package : TQFP144 ### Speed : 4 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = top_level. Target frequency = 54.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /usr/local/diamond/3.12/ispfpga/xo2c00/data (searchpath added) -p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/build (searchpath added) -p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga (searchpath added) VHDL library = work VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_MODULE_CONFIG.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_CROSSBAR_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/spi/SPI_R_DRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_D_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_TX_SDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_RX_SDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_STD_ENCODER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_S_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_TX_DDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_STD_DECODER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_RX_DDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_T_CONTROLLER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_R_CONTROLLER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_C_DIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_C_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/GPIO_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/PWM_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/LED_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE_ENCODER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/StepperControl.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/EMAGNET_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/time_sensitive_emulation/time_sensitive_CU.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/time_sensitive_emulation/time_sensitive_PS.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_TABLE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_UNIT.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/STREAM_FIFO.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/ROM16XN_FIFO.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_T_UNIT.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_T_TABLE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/IO_CROSSBAR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/LOW_DEBOUNCE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/EDGE_DETECTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/ENCODER_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/CLOCK_DIVIDER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/ENCODER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_CROSSBAR_CONFIG.vhd NGD file = Project_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. -vh2008 Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file /usr/local/diamond/3.12/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin INFO - synthesis: The default VHDL library search path is now "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/build". VHDL-1504 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(5): analyzing package goldi_comm_standard. VHDL-1014 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(197): analyzing package body goldi_comm_standard. VHDL-1013 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd(5): analyzing package goldi_io_standard. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_MODULE_CONFIG.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_MODULE_CONFIG.vhd(11): analyzing package goldi_module_config. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_CROSSBAR_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_CROSSBAR_STANDARD.vhd(6): analyzing package goldi_crossbar_standard. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_CROSSBAR_CONFIG.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/GOLDI_CROSSBAR_CONFIG.vhd(12): analyzing package goldi_crossbar_config. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER.vhd(10): analyzing entity synchronizer. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER.vhd(23): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(18): analyzing entity sp_converter. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(39): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(42): analyzing entity bus_adaptor. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(60): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(42): analyzing entity goldi_spi_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(59): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_UNIT.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_UNIT.vhd(32): analyzing entity register_unit. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_UNIT.vhd(53): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER.vhd(15): analyzing entity tris_buffer. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER.vhd(30): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(10): analyzing entity tris_buffer_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(28): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_TABLE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_TABLE.vhd(42): analyzing entity register_table. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_TABLE.vhd(64): analyzing architecture bh. VHDL-1010 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_TABLE.vhd(143): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/GPIO_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/GPIO_SMODULE.vhd(25): analyzing entity gpio_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/GPIO_SMODULE.vhd(44): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/PWM_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/PWM_SMODULE.vhd(21): analyzing entity pwm_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/PWM_SMODULE.vhd(40): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/LED_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/LED_SMODULE.vhd(35): analyzing entity led_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/LED_SMODULE.vhd(55): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/IO_CROSSBAR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/IO_CROSSBAR.vhd(45): analyzing entity io_crossbar. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/IO_CROSSBAR.vhd(69): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd(22): analyzing entity top_level. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd(42): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd(5): analyzing package goldi_data_types. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd(43): analyzing entity spi_t_driver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd(71): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/spi/SPI_R_DRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/spi/SPI_R_DRIVER.vhd(46): analyzing entity spi_r_driver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/spi/SPI_R_DRIVER.vhd(72): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/STREAM_FIFO.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/STREAM_FIFO.vhd(22): analyzing entity stream_fifo. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/STREAM_FIFO.vhd(42): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_STD_ENCODER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_STD_ENCODER.vhd(30): analyzing entity uart_std_encoder. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_STD_ENCODER.vhd(52): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_TX_DDRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_TX_DDRIVER.vhd(31): analyzing entity uart_tx_ddriver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_TX_DDRIVER.vhd(55): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_RX_DDRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_RX_DDRIVER.vhd(33): analyzing entity uart_rx_ddriver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_RX_DDRIVER.vhd(57): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_STD_DECODER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_STD_DECODER.vhd(29): analyzing entity uart_std_decoder. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_STD_DECODER.vhd(53): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_D_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_D_SMODULE.vhd(59): analyzing entity uart_d_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_D_SMODULE.vhd(86): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_TX_SDRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_TX_SDRIVER.vhd(15): analyzing entity uart_tx_sdriver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_TX_SDRIVER.vhd(36): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_RX_SDRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_RX_SDRIVER.vhd(17): analyzing entity uart_rx_sdriver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_RX_SDRIVER.vhd(38): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_S_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_S_SMODULE.vhd(42): analyzing entity uart_s_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/uart/UART_S_SMODULE.vhd(70): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_T_CONTROLLER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_T_CONTROLLER.vhd(16): analyzing entity i2c_t_controller. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_T_CONTROLLER.vhd(34): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_R_CONTROLLER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_R_CONTROLLER.vhd(14): analyzing entity i2c_r_controller. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_R_CONTROLLER.vhd(31): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_C_DIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_C_DIVER.vhd(34): analyzing entity i2c_c_driver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_C_DIVER.vhd(60): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_T_UNIT.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_T_UNIT.vhd(33): analyzing entity register_t_unit. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_T_UNIT.vhd(57): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_C_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_C_SMODULE.vhd(46): analyzing entity i2c_c_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/comms/i2c/I2C_C_SMODULE.vhd(71): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd(18): analyzing entity tmc2660_config_fifo. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd(34): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/ENCODER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/ENCODER.vhd(38): analyzing entity encoder. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/ENCODER.vhd(56): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/CLOCK_DIVIDER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/CLOCK_DIVIDER.vhd(5): analyzing entity clock_divider. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/CLOCK_DIVIDER.vhd(16): analyzing architecture bhv. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/ROM16XN_FIFO.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/ROM16XN_FIFO.vhd(32): analyzing entity rom16xn_fifo. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/ROM16XN_FIFO.vhd(52): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/StepperControl.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/StepperControl.vhd(19): analyzing entity steppercontrol. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/StepperControl.vhd(35): analyzing architecture behavioral. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd(47): analyzing entity tmc2660_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd(80): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE_ENCODER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE_ENCODER.vhd(8): analyzing entity tmc2660_smodule_encoder. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE_ENCODER.vhd(42): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd(17): analyzing entity tmc2660_spi. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd(40): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/EMAGNET_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/EMAGNET_SMODULE.vhd(27): analyzing entity emagnet_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/EMAGNET_SMODULE.vhd(49): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd(38): analyzing entity hbridge_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd(58): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/time_sensitive_emulation/time_sensitive_CU.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/time_sensitive_emulation/time_sensitive_CU.vhd(12): analyzing entity time_sensitive_cu. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/time_sensitive_emulation/time_sensitive_CU.vhd(32): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/time_sensitive_emulation/time_sensitive_PS.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/time_sensitive_emulation/time_sensitive_PS.vhd(10): analyzing entity time_sensitive_ps. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/time_sensitive_emulation/time_sensitive_PS.vhd(24): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_T_TABLE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_T_TABLE.vhd(38): analyzing entity register_t_table. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_T_TABLE.vhd(63): analyzing architecture bh. VHDL-1010 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/memory/REGISTER_T_TABLE.vhd(143): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd(12): analyzing entity high_debounce. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd(28): analyzing architecture bh. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd(10): analyzing entity synchronizer_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd(24): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/LOW_DEBOUNCE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/LOW_DEBOUNCE.vhd(12): analyzing entity low_debounce. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/io_management/LOW_DEBOUNCE.vhd(28): analyzing architecture bh. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/EDGE_DETECTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/EDGE_DETECTOR.vhd(13): analyzing entity edge_detector. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/EDGE_DETECTOR.vhd(26): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/ENCODER_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/ENCODER_SMODULE.vhd(20): analyzing entity encoder_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/common/dsp/ENCODER_SMODULE.vhd(39): analyzing architecture rtl. VHDL-1010 unit top_level is not yet analyzed. VHDL-1485 /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd(22): executing TOP_LEVEL(RTL) WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/src/TOP_LEVEL.vhd(36): replacing existing netlist TOP_LEVEL(RTL). VHDL-1205 Top module name (VHDL): TOP_LEVEL Last elaborated design is TOP_LEVEL(RTL) Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Top-level module name = TOP_LEVEL. INFO - synthesis: Extracted state machine for register '\SPI_BUS_COMMUNICATION/BUS_INTERFACE/ps_mbus' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 WARNING - synthesis: Bit 1 of Register \TEST/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 2 of Register \TEST/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 6 of Register \TEST/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Skipping pad insertion on IO_DATA[65] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[64] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[63] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[62] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[61] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[60] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[59] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[58] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[57] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[56] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[55] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[54] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[53] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[52] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[51] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[50] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[49] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[48] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[47] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[46] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[45] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[44] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[43] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[42] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[41] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[40] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[39] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[38] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[37] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[36] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[35] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[34] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[33] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[32] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[31] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[30] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[29] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[28] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[27] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[26] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[25] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[24] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[23] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[22] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[21] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[20] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[19] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[18] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[17] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[16] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[15] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[14] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[13] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[12] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[11] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[10] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[9] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[8] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[7] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[6] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[5] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[4] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[3] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[2] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[1] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[0] due to black_box_pad_pin attribute. Duplicate register/latch removal. \TEST/sys_bus_o.dat_i1 is a one-to-one match with \TEST/sys_bus_o.dat_i2. Duplicate register/latch removal. \TEST/sys_bus_o.dat_i5 is a one-to-one match with \TEST/sys_bus_o.dat_i3. Duplicate register/latch removal. \TEST/sys_bus_o.dat_i4 is a one-to-one match with \TEST/sys_bus_o.dat_i5. Duplicate register/latch removal. \TEST/sys_bus_o.dat_i1 is a one-to-one match with \TEST/sys_bus_o.dat_i4. GSR instance connected to net n9945. Duplicate register/latch removal. \TEST/sys_bus_o.dat_i1 is a one-to-one match with \TEST/sys_bus_o.mux_32. Applying 54.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in TOP_LEVEL_drc.log. Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Running DRC... WARNING - synthesis: logical net 'port_in_async_64_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_65_.dat' has no load. WARNING - synthesis: DRC complete with 2 warnings. Design Results: 6554 blocks expanded completed the first expansion All blocks are expanded and NGD expansion is successful. Writing NGD file Project_impl1.ngd. ################### Begin Area Report (TOP_LEVEL)###################### Number of register bits => 2302 of 7209 (31 % ) BB => 66 CCU2D => 254 FD1P3AX => 1190 FD1P3AY => 194 FD1P3IX => 162 FD1P3JX => 16 FD1S3AX => 195 FD1S3AY => 17 FD1S3IX => 526 FD1S3JX => 2 GSR => 1 IB => 5 L6MUX21 => 374 LUT4 => 2825 OB => 1 PFUMX => 723 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : ClockFPGA_c, loads : 2302 Clock Enable Nets Number of Clock Enables: 271 Top 10 highest fanout Clock Enables: Net : SPI_BUS_COMMUNICATION/BUS_INTERFACE/ClockFPGA_c_enable_563, loads : 10 Net : PWM_SIGNALS_0..PWM_DRIVER/MEMORY/p_data_out_7__N_1610, loads : 9 Net : PWM_SIGNALS_7..PWM_DRIVER/ClockFPGA_c_enable_512, loads : 9 Net : PWM_SIGNALS_11..PWM_DRIVER/ClockFPGA_c_enable_467, loads : 9 Net : PWM_SIGNALS_1..PWM_DRIVER/MEMORY/p_data_out_7__N_1693, loads : 9 Net : PWM_SIGNALS_12..PWM_DRIVER/ClockFPGA_c_enable_455, loads : 9 Net : PWM_SIGNALS_15..PWM_DRIVER/ClockFPGA_c_enable_432, loads : 9 Net : FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1392, loads : 8 Net : FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1308, loads : 8 Net : FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1315, loads : 8 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : SPI_BUS_COMMUNICATION/BUS_INTERFACE/master_bus_o.adr_0, loads : 517 Net : n27854, loads : 281 Net : n27830, loads : 132 Net : sys_bus_i.dat_7, loads : 82 Net : sys_bus_i.dat_6, loads : 82 Net : sys_bus_i.dat_5, loads : 82 Net : sys_bus_i.dat_4, loads : 82 Net : sys_bus_i.dat_3, loads : 82 Net : sys_bus_i.dat_2, loads : 82 Net : sys_bus_i.dat_1, loads : 82 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 18.518519 -name | | | clk0 [get_nets ClockFPGA_c] | 54.001 MHz| 53.482 MHz| 11 * | | | -------------------------------------------------------------------------------- 1 constraints not met. Peak Memory Usage: 287.574 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 9.680 secs -------------------------------------------------------------- Nothing is executed for the "Translate" process map -a "MachXO2" -p LCMXO2-7000HC -t TQFP144 -s 4 -oc Commercial "Project_impl1.ngd" -o "Project_impl1_map.ncd" -pr "Project_impl1.prf" -mp "Project_impl1.mrp" -lpf "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/build/Project_impl1.lpf" -lpf "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/mole/fpga/constraints.lpf" -c 0 map: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Process the file: Project_impl1.ngd Picdevice="LCMXO2-7000HC" Pictype="TQFP144" Picspeed=4 Remove unused logic Do not produce over sized NCDs. Part used: LCMXO2-7000HCTQFP144, Performance used: 4. Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Running general design DRC... Removing unused logic... Optimizing... Design Summary: Number of registers: 2302 out of 7209 (32%) PFU registers: 2302 out of 6864 (34%) PIO registers: 0 out of 345 (0%) Number of SLICEs: 1935 out of 3432 (56%) SLICEs as Logic/ROM: 1935 out of 3432 (56%) SLICEs as RAM: 0 out of 2574 (0%) SLICEs as Carry: 254 out of 3432 (7%) Number of LUT4s: 3332 out of 6864 (49%) Number used as logic LUTs: 2824 Number used as distributed RAM: 0 Number used as ripple logic: 508 Number used as shift registers: 0 Number of PIO sites used: 72 + 4(JTAG) out of 115 (66%) Number of block RAMs: 0 out of 26 (0%) Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 2 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 1 Net ClockFPGA_c: 1308 loads, 1308 rising, 0 falling (Driver: PIO ClockFPGA ) Number of Clock Enables: 271 Net ClockFPGA_c_enable_274: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_687: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_659: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_639: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_637: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_648: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_646: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_108: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_196: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_136: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_202: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_204: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_573: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_586: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_621: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_593: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_575: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_208: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_335: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_337: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_328: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_300: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_307: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_414: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_579: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_900: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_921: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_893: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_874: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_884: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_876: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_880: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_826: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_868: 8 loads, 8 LSLICEs Net ClockFPGA_c_enable_812: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_854: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_840: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_728: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_732: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_753: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_767: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_710: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_781: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_739: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_746: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_788: 8 loads, 8 LSLICEs Net ClockFPGA_c_enable_644: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_652: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_87: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_64: 8 loads, 8 LSLICEs Net ClockFPGA_c_enable_159: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_181: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_200: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_8/ClockFPGA_c_enable_870: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_878: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_8/ClockFPGA_c_enable_882: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_8/ClockFPGA_c_enable_886: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_907: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_914: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_8/ClockFPGA_c_enable_928: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_935: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_942: 8 loads, 8 LSLICEs Net ClockFPGA_c_enable_198: 2 loads, 2 LSLICEs Net p_data_out_7__N_270: 6 loads, 6 LSLICEs Net ClockFPGA_c_enable_416: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_412: 2 loads, 2 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_949: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_958: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_972: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1028: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1084: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1140: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1196: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1252: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1308: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1007: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1063: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1119: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1175: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1231: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1287: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1343: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_965: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_979: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_986: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_993: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1000: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1014: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1021: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1035: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1042: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1049: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1056: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1070: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1077: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1091: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1098: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1105: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1112: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1126: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1133: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1147: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1154: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1161: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1168: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1182: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1189: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1203: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1210: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1217: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1224: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1238: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1245: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1259: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1266: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1273: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1280: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1294: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1301: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1315: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1322: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1329: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1336: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1350: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1357: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1364: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1371: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1378: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1385: 4 loads, 4 LSLICEs Net FPGA_GPIOs/MEMORY/ClockFPGA_c_enable_1392: 4 loads, 4 LSLICEs Net p_data_out_7__N_1859: 4 loads, 4 LSLICEs Net PWM_SIGNALS_8..PWM_DRIVER/ClockFPGA_c_enable_481: 1 loads, 1 LSLICEs Net PWM_SIGNALS_8..PWM_DRIVER/ClockFPGA_c_enable_505: 4 loads, 4 LSLICEs Net p_data_out_7__N_2274: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_279: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_277: 2 loads, 2 LSLICEs Net PWM_SIGNALS_9..PWM_DRIVER/ClockFPGA_c_enable_491: 4 loads, 4 LSLICEs Net PWM_SIGNALS_9..PWM_DRIVER/ClockFPGA_c_enable_480: 1 loads, 1 LSLICEs Net p_data_out_7__N_2357: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_872: 2 loads, 2 LSLICEs Net PWM_SIGNALS_13..PWM_DRIVER/ClockFPGA_c_enable_446: 4 loads, 4 LSLICEs Net PWM_SIGNALS_13..PWM_DRIVER/ClockFPGA_c_enable_487: 1 loads, 1 LSLICEs Net p_data_out_7__N_2689: 4 loads, 4 LSLICEs Net PWM_SIGNALS_12..PWM_DRIVER/ClockFPGA_c_enable_455: 4 loads, 4 LSLICEs Net PWM_SIGNALS_12..PWM_DRIVER/ClockFPGA_c_enable_488: 1 loads, 1 LSLICEs Net p_data_out_7__N_2606: 4 loads, 4 LSLICEs Net PWM_SIGNALS_11..PWM_DRIVER/ClockFPGA_c_enable_467: 4 loads, 4 LSLICEs Net PWM_SIGNALS_11..PWM_DRIVER/ClockFPGA_c_enable_495: 1 loads, 1 LSLICEs Net p_data_out_7__N_2523: 4 loads, 4 LSLICEs Net PWM_SIGNALS_10..PWM_DRIVER/ClockFPGA_c_enable_475: 4 loads, 4 LSLICEs Net PWM_SIGNALS_10..PWM_DRIVER/ClockFPGA_c_enable_499: 1 loads, 1 LSLICEs Net p_data_out_7__N_2440: 4 loads, 4 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/ClockFPGA_c_enable_561: 4 loads, 4 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/ClockFPGA_c_enable_797: 1 loads, 1 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/MEMORY/p_data_out_7__N_1610: 4 loads, 4 LSLICEs Net p_data_out_7__N_1942: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_774: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_760: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_804: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_380: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_408: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_401: 4 loads, 4 LSLICEs Net p_data_out_7__N_1776: 4 loads, 4 LSLICEs Net POWER_RED/blink_counter_enb: 4 loads, 4 LSLICEs Net p_data_out_7__N_2957: 4 loads, 4 LSLICEs Net PWM_SIGNALS_7..PWM_DRIVER/ClockFPGA_c_enable_482: 1 loads, 1 LSLICEs Net PWM_SIGNALS_7..PWM_DRIVER/ClockFPGA_c_enable_512: 4 loads, 4 LSLICEs Net p_data_out_7__N_2191: 4 loads, 4 LSLICEs Net p_data_out_7__N_2108: 4 loads, 4 LSLICEs Net PWM_SIGNALS_6..PWM_DRIVER/ClockFPGA_c_enable_485: 1 loads, 1 LSLICEs Net PWM_SIGNALS_6..PWM_DRIVER/ClockFPGA_c_enable_519: 4 loads, 4 LSLICEs Net PWM_SIGNALS_5..PWM_DRIVER/ClockFPGA_c_enable_486: 1 loads, 1 LSLICEs Net PWM_SIGNALS_5..PWM_DRIVER/ClockFPGA_c_enable_526: 4 loads, 4 LSLICEs Net p_data_out_7__N_2025: 4 loads, 4 LSLICEs Net PWM_SIGNALS_4..PWM_DRIVER/ClockFPGA_c_enable_493: 1 loads, 1 LSLICEs Net PWM_SIGNALS_4..PWM_DRIVER/ClockFPGA_c_enable_533: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_680: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_708: 8 loads, 8 LSLICEs Net ClockFPGA_c_enable_673: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_701: 4 loads, 4 LSLICEs Net POWER_GREEN/blink_counter_enb: 4 loads, 4 LSLICEs Net p_data_out_7__N_3059: 4 loads, 4 LSLICEs Net PWM_SIGNALS_3..PWM_DRIVER/ClockFPGA_c_enable_497: 1 loads, 1 LSLICEs Net PWM_SIGNALS_3..PWM_DRIVER/ClockFPGA_c_enable_540: 4 loads, 4 LSLICEs Net p_data_out_7__N_2855: 4 loads, 4 LSLICEs Net PWM_SIGNALS_2..PWM_DRIVER/ClockFPGA_c_enable_547: 4 loads, 4 LSLICEs Net PWM_SIGNALS_2..PWM_DRIVER/ClockFPGA_c_enable_795: 1 loads, 1 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/ClockFPGA_c_enable_554: 4 loads, 4 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/ClockFPGA_c_enable_796: 1 loads, 1 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/MEMORY/p_data_out_7__N_1693: 4 loads, 4 LSLICEs Net PWM_SIGNALS_15..PWM_DRIVER/ClockFPGA_c_enable_432: 4 loads, 4 LSLICEs Net PWM_SIGNALS_15..PWM_DRIVER/ClockFPGA_c_enable_483: 1 loads, 1 LSLICEs Net PWM_SIGNALS_14..PWM_DRIVER/ClockFPGA_c_enable_439: 4 loads, 4 LSLICEs Net PWM_SIGNALS_14..PWM_DRIVER/ClockFPGA_c_enable_484: 1 loads, 1 LSLICEs Net p_data_out_7__N_2772: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_206: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_614: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_628: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_600: 4 loads, 4 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_800: 3 loads, 3 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_720: 4 loads, 4 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_951: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_423: 2 loads, 2 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_1: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_114: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_567: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_566: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_564: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_565: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_640: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_714: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_794: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_3: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_271: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_272: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_273: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_275: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_424: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_426: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_448: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_449: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_457: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_458: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/BUS_INTERFACE/ClockFPGA_c_enable_563: 5 loads, 5 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_53: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_56: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_569: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_571: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_577: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_607: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_4/ClockFPGA_c_enable_635: 8 loads, 8 LSLICEs Net IO_ROUTING_BANK_3/ClockFPGA_c_enable_189: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_642: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_650: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_694: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_5/ClockFPGA_c_enable_666: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_343: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_341: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_339: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_347: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_351: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_349: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_345: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_321: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_314: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_293: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_2/ClockFPGA_c_enable_286: 8 loads, 8 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_420: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_418: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_410: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_394: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_387: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_372: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_365: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_358: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_1/ClockFPGA_c_enable_1394: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_726: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_730: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_712: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_722: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_6/ClockFPGA_c_enable_724: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_847: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_819: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_806: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_808: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_810: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_790: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_792: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_802: 2 loads, 2 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_833: 4 loads, 4 LSLICEs Net IO_ROUTING_BANK_7/ClockFPGA_c_enable_861: 4 loads, 4 LSLICEs Number of LSRs: 67 Net n27944: 16 loads, 16 LSLICEs Net n9973: 8 loads, 8 LSLICEs Net n9994: 8 loads, 8 LSLICEs Net n9969: 8 loads, 8 LSLICEs Net n9967: 8 loads, 8 LSLICEs Net n9968: 8 loads, 8 LSLICEs Net n9965: 8 loads, 8 LSLICEs Net n9963: 8 loads, 8 LSLICEs Net n9966: 8 loads, 8 LSLICEs Net n27721: 4 loads, 4 LSLICEs Net n9964: 8 loads, 8 LSLICEs Net n27733: 4 loads, 4 LSLICEs Net PWM_SIGNALS_8..PWM_DRIVER/n3510: 9 loads, 9 LSLICEs Net PWM_SIGNALS_8..PWM_DRIVER/n3513: 5 loads, 5 LSLICEs Net n27731: 4 loads, 4 LSLICEs Net PWM_SIGNALS_9..PWM_DRIVER/n3517: 9 loads, 9 LSLICEs Net PWM_SIGNALS_9..PWM_DRIVER/n3520: 5 loads, 5 LSLICEs Net n27730: 4 loads, 4 LSLICEs Net PWM_SIGNALS_13..PWM_DRIVER/n3545: 9 loads, 9 LSLICEs Net PWM_SIGNALS_13..PWM_DRIVER/n3548: 5 loads, 5 LSLICEs Net n27727: 4 loads, 4 LSLICEs Net PWM_SIGNALS_12..PWM_DRIVER/n3538: 9 loads, 9 LSLICEs Net PWM_SIGNALS_12..PWM_DRIVER/n3541: 5 loads, 5 LSLICEs Net n27728: 4 loads, 4 LSLICEs Net PWM_SIGNALS_11..PWM_DRIVER/n3531: 9 loads, 9 LSLICEs Net PWM_SIGNALS_11..PWM_DRIVER/n3534: 5 loads, 5 LSLICEs Net n27709: 4 loads, 4 LSLICEs Net PWM_SIGNALS_10..PWM_DRIVER/n3524: 9 loads, 9 LSLICEs Net PWM_SIGNALS_10..PWM_DRIVER/n3527: 5 loads, 5 LSLICEs Net n27729: 4 loads, 4 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/n3454: 9 loads, 9 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/n3457: 5 loads, 5 LSLICEs Net PWM_SIGNALS_0..PWM_DRIVER/MEMORY/n27739: 4 loads, 4 LSLICEs Net n27745: 4 loads, 4 LSLICEs Net n27746: 4 loads, 4 LSLICEs Net POWER_RED/led_counter_21__N_2919: 12 loads, 12 LSLICEs Net n27725: 4 loads, 4 LSLICEs Net PWM_SIGNALS_7..PWM_DRIVER/n3503: 9 loads, 9 LSLICEs Net PWM_SIGNALS_7..PWM_DRIVER/n3506: 5 loads, 5 LSLICEs Net n27732: 4 loads, 4 LSLICEs Net n27710: 4 loads, 4 LSLICEs Net PWM_SIGNALS_6..PWM_DRIVER/n3496: 9 loads, 9 LSLICEs Net PWM_SIGNALS_6..PWM_DRIVER/n3499: 5 loads, 5 LSLICEs Net PWM_SIGNALS_5..PWM_DRIVER/n3489: 9 loads, 9 LSLICEs Net PWM_SIGNALS_5..PWM_DRIVER/n3492: 5 loads, 5 LSLICEs Net n27743: 4 loads, 4 LSLICEs Net PWM_SIGNALS_4..PWM_DRIVER/n3482: 9 loads, 9 LSLICEs Net PWM_SIGNALS_4..PWM_DRIVER/n3485: 5 loads, 5 LSLICEs Net POWER_GREEN/led_counter_21__N_3021: 12 loads, 12 LSLICEs Net n27724: 4 loads, 4 LSLICEs Net PWM_SIGNALS_3..PWM_DRIVER/n3475: 9 loads, 9 LSLICEs Net PWM_SIGNALS_3..PWM_DRIVER/n3478: 5 loads, 5 LSLICEs Net n27708: 4 loads, 4 LSLICEs Net PWM_SIGNALS_2..PWM_DRIVER/n3468: 9 loads, 9 LSLICEs Net PWM_SIGNALS_2..PWM_DRIVER/n3471: 5 loads, 5 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/n3461: 9 loads, 9 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/n3464: 5 loads, 5 LSLICEs Net PWM_SIGNALS_1..PWM_DRIVER/MEMORY/n27734: 4 loads, 4 LSLICEs Net PWM_SIGNALS_15..PWM_DRIVER/n3559: 9 loads, 9 LSLICEs Net PWM_SIGNALS_15..PWM_DRIVER/n3562: 5 loads, 5 LSLICEs Net PWM_SIGNALS_14..PWM_DRIVER/n3552: 9 loads, 9 LSLICEs Net PWM_SIGNALS_14..PWM_DRIVER/n3555: 5 loads, 5 LSLICEs Net n27726: 4 loads, 4 LSLICEs Net SPI_BUS_COMMUNICATION/n6904: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/p_master_bus_o.adr_9__N_231: 10 loads, 10 LSLICEs Net SPI_BUS_COMMUNICATION/n27957: 12 loads, 12 LSLICEs Net SPI_BUS_COMMUNICATION/n6907: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net master_bus_o.adr_0: 519 loads Net n27854: 281 loads Net n27830: 132 loads Net sys_bus_i.dat_0: 82 loads Net sys_bus_i.dat_1: 82 loads Net sys_bus_i.dat_2: 82 loads Net sys_bus_i.dat_3: 82 loads Net sys_bus_i.dat_4: 82 loads Net sys_bus_i.dat_5: 82 loads Net sys_bus_i.dat_6: 82 loads Number of warnings: 0 Number of errors: 0 Total CPU Time: 4 secs Total REAL Time: 9 secs Peak Memory Usage: 217 MB Dumping design to file Project_impl1_map.ncd. ncd2vdb "Project_impl1_map.ncd" ".vdbs/Project_impl1_map.vdb" Loading device for application ncd2vdb from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. mpartrce -p "Project_impl1.p2t" -f "Project_impl1.p3t" -tf "Project_impl1.pt" "Project_impl1_map.ncd" "Project_impl1.ncd" ---- MParTrce Tool ---- Removing old design directory at request of -rem command line option to this program. Running par. Please wait . . . Lattice Place and Route Report for Design "Project_impl1_map.ncd" Wed Sep 24 14:19:18 2025 PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 Project_impl1_map.ncd Project_impl1.dir/5_1.ncd Project_impl1.prf Preference file: Project_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file Project_impl1_map.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 72+4(JTAG)/336 23% used 72+4(JTAG)/115 66% bonded SLICE 1935/3432 56% used GSR 1/1 100% used Number of Signals: 5503 Number of Connections: 17403 Pin Constraint Summary: 72 out of 72 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: ClockFPGA_c (driver: ClockFPGA, clk load #: 1308) The following 5 signals are selected to use the secondary clock routing resources: n27944 (driver: SLICE_577, clk load #: 0, sr load #: 16, ce load #: 0) POWER_RED/led_counter_21__N_2919 (driver: SLICE_460, clk load #: 0, sr load #: 12, ce load #: 0) POWER_GREEN/led_counter_21__N_3021 (driver: SLICE_451, clk load #: 0, sr load #: 12, ce load #: 0) SPI_BUS_COMMUNICATION/n27957 (driver: SLICE_2529, clk load #: 0, sr load #: 12, ce load #: 0) SPI_BUS_COMMUNICATION/p_master_bus_o.adr_9__N_231 (driver: SLICE_576, clk load #: 0, sr load #: 10, ce load #: 0) Signal RESET_SYNC/FPGA_nReset_sync is selected as Global Set/Reset. Starting Placer Phase 0. .......... Finished Placer Phase 0. REAL time: 7 secs Starting Placer Phase 1. ...................... Placer score = 1537644. Finished Placer Phase 1. REAL time: 31 secs Starting Placer Phase 2. . Placer score = 1524254 Finished Placer Phase 2. REAL time: 34 secs ------------------ Clock Report ------------------ Global Clock Resources: CLK_PIN : 1 out of 8 (12%) PLL : 0 out of 2 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: PRIMARY "ClockFPGA_c" from comp "ClockFPGA" on CLK_PIN site "128 (PT18A)", clk load = 1308 SECONDARY "n27944" from F1 on comp "SLICE_577" on site "R21C18D", clk load = 0, ce load = 0, sr load = 16 SECONDARY "POWER_RED/led_counter_21__N_2919" from F0 on comp "SLICE_460" on site "R14C18B", clk load = 0, ce load = 0, sr load = 12 SECONDARY "POWER_GREEN/led_counter_21__N_3021" from F0 on comp "SLICE_451" on site "R14C20B", clk load = 0, ce load = 0, sr load = 12 SECONDARY "SPI_BUS_COMMUNICATION/n27957" from F0 on comp "SLICE_2529" on site "R21C18A", clk load = 0, ce load = 0, sr load = 12 SECONDARY "SPI_BUS_COMMUNICATION/p_master_bus_o.adr_9__N_231" from Q0 on comp "SLICE_576" on site "R14C18D", clk load = 0, ce load = 0, sr load = 10 PRIMARY : 1 out of 8 (12%) SECONDARY: 5 out of 8 (62%) Edge Clocks: No edge clock selected. --------------- End of Clock Report --------------- I/O Usage Summary (final): 72 + 4(JTAG) out of 336 (22.6%) PIO sites used. 72 + 4(JTAG) out of 115 (66.1%) bonded PIO sites used. Number of PIO comps: 72; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ | 0 | 3 / 28 ( 10%) | 3.3V | - | | 1 | 24 / 29 ( 82%) | 3.3V | - | | 2 | 21 / 29 ( 72%) | 3.3V | - | | 3 | 9 / 9 (100%) | 3.3V | - | | 4 | 10 / 10 (100%) | 3.3V | - | | 5 | 5 / 10 ( 50%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 16 secs Dumping design to file Project_impl1.dir/5_1.ncd. 0 connections routed; 17403 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 40 secs Start NBR router at Wed Sep 24 14:19:58 UTC 2025 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at Wed Sep 24 14:19:59 UTC 2025 Start NBR section for initial routing at Wed Sep 24 14:19:59 UTC 2025 Level 1, iteration 1 0(0.00%) conflict; 14349(82.45%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 2.390ns/0.000ns; real time: 42 secs Level 2, iteration 1 2(0.00%) conflicts; 14342(82.41%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 2.580ns/0.000ns; real time: 42 secs Level 3, iteration 1 6(0.00%) conflicts; 13889(79.81%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 3.422ns/0.000ns; real time: 45 secs Level 4, iteration 1 1159(0.31%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 3.487ns/0.000ns; real time: 52 secs Info: Initial congestion level at 75% usage is 8 Info: Initial congestion area at 75% usage is 173 (17.30%) Start NBR section for normal routing at Wed Sep 24 14:20:10 UTC 2025 Level 1, iteration 1 1(0.00%) conflict; 1778(10.22%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 3.413ns/0.000ns; real time: 53 secs Level 4, iteration 1 626(0.17%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.415ns/0.000ns; real time: 59 secs Level 4, iteration 2 384(0.10%) conflicts; 0(0.00%) untouched conn; 861 (nbr) score; Estimated worst slack/total negative slack: -0.123ns/-0.861ns; real time: 1 mins 5 secs Level 4, iteration 3 218(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.031ns/0.000ns; real time: 1 mins 8 secs Level 4, iteration 4 182(0.05%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.031ns/0.000ns; real time: 1 mins 11 secs Level 4, iteration 5 177(0.05%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 0.545ns/0.000ns; real time: 1 mins 14 secs Level 4, iteration 6 107(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 0.545ns/0.000ns; real time: 1 mins 16 secs Level 4, iteration 7 81(0.02%) conflicts; 0(0.00%) untouched conn; 7644 (nbr) score; Estimated worst slack/total negative slack: -0.998ns/-7.644ns; real time: 1 mins 17 secs Level 4, iteration 8 64(0.02%) conflicts; 0(0.00%) untouched conn; 7644 (nbr) score; Estimated worst slack/total negative slack: -0.998ns/-7.644ns; real time: 1 mins 19 secs Level 4, iteration 9 35(0.01%) conflicts; 0(0.00%) untouched conn; 1751 (nbr) score; Estimated worst slack/total negative slack: -0.308ns/-1.751ns; real time: 1 mins 19 secs Level 4, iteration 10 34(0.01%) conflicts; 0(0.00%) untouched conn; 1751 (nbr) score; Estimated worst slack/total negative slack: -0.308ns/-1.751ns; real time: 1 mins 20 secs Level 4, iteration 11 26(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 1 mins 21 secs Level 4, iteration 12 27(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 1 mins 22 secs Level 4, iteration 13 17(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 1 mins 23 secs Level 4, iteration 14 8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 1 mins 23 secs Level 4, iteration 15 5(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 1 mins 24 secs Level 4, iteration 16 5(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 1 mins 25 secs Level 4, iteration 17 5(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 1 mins 25 secs Level 4, iteration 18 13(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 1 mins 26 secs Level 4, iteration 19 5(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 1 mins 26 secs Level 4, iteration 20 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.463ns/0.000ns; real time: 1 mins 26 secs Level 4, iteration 21 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.477ns/0.000ns; real time: 1 mins 27 secs Level 4, iteration 22 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.477ns/0.000ns; real time: 1 mins 27 secs Level 4, iteration 23 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.477ns/0.000ns; real time: 1 mins 27 secs Level 4, iteration 24 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.477ns/0.000ns; real time: 1 mins 27 secs Level 4, iteration 25 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.477ns/0.000ns; real time: 1 mins 28 secs Level 4, iteration 26 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.477ns/0.000ns; real time: 1 mins 28 secs Level 4, iteration 27 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.477ns/0.000ns; real time: 1 mins 28 secs Level 4, iteration 28 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.477ns/0.000ns; real time: 1 mins 28 secs Start NBR section for setup/hold timing optimization with effort level 3 at Wed Sep 24 14:20:46 UTC 2025 Start NBR section for re-routing at Wed Sep 24 14:20:48 UTC 2025 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.477ns/0.000ns; real time: 1 mins 30 secs Start NBR section for post-routing at Wed Sep 24 14:20:48 UTC 2025 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack : 1.477ns Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 47 secs Total REAL time: 1 mins 35 secs Completely routed. End of route. 17403 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file Project_impl1.dir/5_1.ncd. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack> = 1.477 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Worst slack> = 0.304 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 48 secs Total REAL time to completion: 1 mins 37 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Exiting par with exit code 0 Exiting mpartrce with exit code 0 trce -f "Project_impl1.pt" -o "Project_impl1.twr" "Project_impl1.ncd" "Project_impl1.prf" trce: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application trce from file Project_impl1.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 Wed Sep 24 14:20:59 2025 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Project_impl1.twr Project_impl1.ncd Project_impl1.prf Design file: Project_impl1.ncd Preference file: Project_impl1.prf Device,speed: LCMXO2-7000HC,4 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 58522 paths, 1 nets, and 14254 connections (81.91% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 Wed Sep 24 14:21:00 2025 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Project_impl1.twr Project_impl1.ncd Project_impl1.prf Design file: Project_impl1.ncd Preference file: Project_impl1.prf Device,speed: LCMXO2-7000HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 58522 paths, 1 nets, and 14254 connections (81.91% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Total CPU Time: 1 secs Total REAL Time: 2 secs Peak Memory Usage: 180 MB Nothing is executed for the "PAR - PARTrace" process tmcheck -par "Project_impl1.par" bitgen -f "Project_impl1.t2b" -w "Project_impl1.ncd" "Project_impl1.prf" BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application Bitgen from file Project_impl1.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Running DRC. DRC detected 0 errors and 0 warnings. Reading Preference File from Project_impl1.prf. Preference Summary: +---------------------------------+---------------------------------+ | Preference | Current Setting | +---------------------------------+---------------------------------+ | RamCfg | Reset** | +---------------------------------+---------------------------------+ | MCCLK_FREQ | 2.08** | +---------------------------------+---------------------------------+ | CONFIG_SECURE | OFF** | +---------------------------------+---------------------------------+ | INBUF | ON** | +---------------------------------+---------------------------------+ | JTAG_PORT | ENABLE** | +---------------------------------+---------------------------------+ | SDM_PORT | DISABLE** | +---------------------------------+---------------------------------+ | SLAVE_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MASTER_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | I2C_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MUX_CONFIGURATION_PORTS | DISABLE** | +---------------------------------+---------------------------------+ | CONFIGURATION | CFG** | +---------------------------------+---------------------------------+ | COMPRESS_CONFIG | ON** | +---------------------------------+---------------------------------+ | MY_ASSP | OFF** | +---------------------------------+---------------------------------+ | ONE_TIME_PROGRAM | OFF** | +---------------------------------+---------------------------------+ | ENABLE_TRANSFR | DISABLE** | +---------------------------------+---------------------------------+ | SHAREDEBRINIT | DISABLE** | +---------------------------------+---------------------------------+ | BACKGROUND_RECONFIG | OFF** | +---------------------------------+---------------------------------+ * Default setting. ** The specified setting matches the default setting. Creating bit map... Bitstream Status: Final Version 1.95. Saving bit stream in "Project_impl1.bit". Total CPU Time: 3 secs Total REAL Time: 7 secs Peak Memory Usage: 440 MB RTNETLINK answers: File exists Lattice Diamond Deployment Tool 3.12 Command Line Loading Programmer Device Database... Generating SVF..... Reading Input File: build/Project_impl1.bit Output File: dist/bitstream.svf Generate Single SVF file: Start Device 1 LCMXO2-7000HC:SRAM Erase,Program,Verify Build SVF File Operation: Successful. Lattice Diamond Deployment Tool has exited successfully.