RTNETLINK answers: File exists synthesis -f "Project_impl1_lattice.synproj" synthesis: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Tue Aug 27 09:31:14 2024 Command Line: synthesis -f Project_impl1_lattice.synproj INFO - synthesis: Lattice Synthesis Engine Launched. Synthesis options: The -a option is MachXO2. The -s option is 4. The -t option is TQFP144. The -d option is LCMXO2-7000HC. Using package TQFP144. Using performance grade 4. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-7000HC ### Package : TQFP144 ### Speed : 4 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = top_level. Target frequency = 54.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /usr/local/diamond/3.12/ispfpga/xo2c00/data (searchpath added) -p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/build (searchpath added) -p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga (searchpath added) VHDL library = work VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK_D.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/WH_SENSOR_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/GOLDI_MODULE_CONFIG.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR_D.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_CROSSBAR_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_R_DRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_D_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_TX_SDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_RX_SDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_STD_ENCODER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_S_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_TX_DDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_STD_DECODER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_RX_DDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_T_CONTROLLER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_R_CONTROLLER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_C_DIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_C_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/PWM_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/LED_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/StepperControl_v1_00.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/Divider1MioByX_v1_00.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/EMAGNET_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_TABLE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_UNIT.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/STREAM_FIFO.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_UNIT.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_TABLE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/IO_CROSSBAR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/LOW_DEBOUNCE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/EDGE_DETECTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/VIRTUAL_SENSOR_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_DRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/US_SENSOR_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/MAVG_2N_FILTER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/FREQUENCY_ANALYSER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/VIRTUAL_LIMIT_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/PWM_ANALYSER_SMODULE.vhd NGD file = Project_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. -vh2008 Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file /usr/local/diamond/3.12/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin INFO - synthesis: The default VHDL library search path is now "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/build". VHDL-1504 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(39): analyzing package goldi_comm_standard. VHDL-1014 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(255): analyzing package body goldi_comm_standard. VHDL-1013 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd(32): analyzing package goldi_io_standard. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd(32): analyzing package goldi_data_types. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/GOLDI_MODULE_CONFIG.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/GOLDI_MODULE_CONFIG.vhd(40): analyzing package goldi_module_config. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd(42): analyzing entity high_debounce. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd(61): analyzing architecture bh. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_DRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_DRIVER.vhd(56): analyzing entity encoder_driver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_DRIVER.vhd(76): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_UNIT.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_UNIT.vhd(63): analyzing entity register_unit. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_UNIT.vhd(87): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_TABLE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_TABLE.vhd(82): analyzing entity register_table. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_TABLE.vhd(107): analyzing architecture bh. VHDL-1010 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_TABLE.vhd(196): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK_D.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK_D.vhd(72): analyzing entity actuator_mask_d. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK_D.vhd(99): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/VIRTUAL_SENSOR_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/VIRTUAL_SENSOR_ARRAY.vhd(61): analyzing entity virtual_sensor_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/VIRTUAL_SENSOR_ARRAY.vhd(83): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR.vhd(51): analyzing entity error_detector. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR.vhd(78): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/WH_SENSOR_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/WH_SENSOR_ARRAY.vhd(69): analyzing entity wh_sensor_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/WH_SENSOR_ARRAY.vhd(106): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/VIRTUAL_LIMIT_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/VIRTUAL_LIMIT_ARRAY.vhd(70): analyzing entity virtual_limit_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/VIRTUAL_LIMIT_ARRAY.vhd(95): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK.vhd(49): analyzing entity actuator_mask. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK.vhd(78): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR_D.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR_D.vhd(52): analyzing entity error_detector_d. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR_D.vhd(78): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd(38): analyzing entity synchronizer. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd(54): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(47): analyzing entity sp_converter. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(71): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(75): analyzing entity bus_adaptor. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(96): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(77): analyzing entity goldi_spi_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(97): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd(42): analyzing entity tris_buffer. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd(60): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(42): analyzing entity tris_buffer_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(63): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd(89): analyzing entity encoder_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd(113): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd(60): analyzing entity gpio_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd(82): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd(56): analyzing entity rom16xn_fifo. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd(78): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/STREAM_FIFO.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/STREAM_FIFO.vhd(51): analyzing entity stream_fifo. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/STREAM_FIFO.vhd(74): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd(64): analyzing entity spi_t_driver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd(95): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/StepperControl_v1_00.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/StepperControl_v1_00.vhd(29): analyzing entity steppercontrol_v1_00. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/StepperControl_v1_00.vhd(45): analyzing architecture behavioral. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd(74): analyzing entity tmc2660_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd(105): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd(71): analyzing entity hbridge_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd(94): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/LED_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/LED_SMODULE.vhd(71): analyzing entity led_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/LED_SMODULE.vhd(93): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd(54): analyzing entity top_level. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd(74): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_CROSSBAR_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_CROSSBAR_STANDARD.vhd(40): analyzing package goldi_crossbar_standard. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_R_DRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_R_DRIVER.vhd(67): analyzing entity spi_r_driver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_R_DRIVER.vhd(96): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_STD_ENCODER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_STD_ENCODER.vhd(51): analyzing entity uart_std_encoder. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_STD_ENCODER.vhd(76): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_TX_DDRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_TX_DDRIVER.vhd(52): analyzing entity uart_tx_ddriver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_TX_DDRIVER.vhd(79): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_RX_DDRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_RX_DDRIVER.vhd(54): analyzing entity uart_rx_ddriver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_RX_DDRIVER.vhd(81): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_STD_DECODER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_STD_DECODER.vhd(50): analyzing entity uart_std_decoder. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_STD_DECODER.vhd(77): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_D_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_D_SMODULE.vhd(89): analyzing entity uart_d_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_D_SMODULE.vhd(119): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_TX_SDRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_TX_SDRIVER.vhd(36): analyzing entity uart_tx_sdriver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_TX_SDRIVER.vhd(60): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_RX_SDRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_RX_SDRIVER.vhd(38): analyzing entity uart_rx_sdriver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_RX_SDRIVER.vhd(62): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_S_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_S_SMODULE.vhd(72): analyzing entity uart_s_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_S_SMODULE.vhd(103): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_T_CONTROLLER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_T_CONTROLLER.vhd(37): analyzing entity i2c_t_controller. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_T_CONTROLLER.vhd(58): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_R_CONTROLLER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_R_CONTROLLER.vhd(35): analyzing entity i2c_r_controller. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_R_CONTROLLER.vhd(55): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_C_DIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_C_DIVER.vhd(55): analyzing entity i2c_c_driver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_C_DIVER.vhd(84): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_UNIT.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_UNIT.vhd(56): analyzing entity register_t_unit. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_UNIT.vhd(83): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_C_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_C_SMODULE.vhd(70): analyzing entity i2c_c_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_C_SMODULE.vhd(98): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/PWM_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/PWM_SMODULE.vhd(49): analyzing entity pwm_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/PWM_SMODULE.vhd(71): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd(44): analyzing entity tmc2660_config_fifo. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd(63): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SD.vhd(30): analyzing entity tmc2660_sd. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SD.vhd(54): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/Divider1MioByX_v1_00.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/Divider1MioByX_v1_00.vhd(30): analyzing entity divider1miobyx_v1_00. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/Divider1MioByX_v1_00.vhd(41): analyzing architecture behavioral. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd(41): analyzing entity tmc2660_spi. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd(67): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/EMAGNET_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/EMAGNET_SMODULE.vhd(64): analyzing entity emagnet_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/EMAGNET_SMODULE.vhd(89): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_TABLE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_TABLE.vhd(62): analyzing entity register_t_table. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_TABLE.vhd(91): analyzing architecture bh. VHDL-1010 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_TABLE.vhd(178): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/IO_CROSSBAR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/IO_CROSSBAR.vhd(79): analyzing entity io_crossbar. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/IO_CROSSBAR.vhd(106): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd(38): analyzing entity synchronizer_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd(55): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/LOW_DEBOUNCE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/LOW_DEBOUNCE.vhd(33): analyzing entity low_debounce. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/LOW_DEBOUNCE.vhd(52): analyzing architecture bh. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/EDGE_DETECTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/EDGE_DETECTOR.vhd(40): analyzing entity edge_detector. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/EDGE_DETECTOR.vhd(56): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/MAVG_2N_FILTER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/MAVG_2N_FILTER.vhd(34): analyzing entity mavg_2n_filter. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/MAVG_2N_FILTER.vhd(55): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/US_SENSOR_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/US_SENSOR_SMODULE.vhd(57): analyzing entity us_sensor_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/US_SENSOR_SMODULE.vhd(79): analyzing architecture bh. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/FREQUENCY_ANALYSER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/FREQUENCY_ANALYSER.vhd(33): analyzing entity frequency_analyser. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/FREQUENCY_ANALYSER.vhd(51): analyzing architecture bh. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/PWM_ANALYSER_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/PWM_ANALYSER_SMODULE.vhd(55): analyzing entity pwm_analyser_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/PWM_ANALYSER_SMODULE.vhd(76): analyzing architecture rtl. VHDL-1010 unit top_level is not yet analyzed. VHDL-1485 /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd(54): executing TOP_LEVEL(RTL) WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd(68): replacing existing netlist TOP_LEVEL(RTL). VHDL-1205 Top module name (VHDL): TOP_LEVEL Last elaborated design is TOP_LEVEL(RTL) Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Top-level module name = TOP_LEVEL. @Inferred core reset on ram net :memory WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd(197): Register \X_ENCODER/enc_block_37 is stuck at Zero. VDB-5013 INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/sCurrentState' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 INFO - synthesis: Extracted state machine for register '\Z_AXIS_MOTOR/sCurrentState' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 INFO - synthesis: Extracted state machine for register '\SPI_BUS_COMMUNICATION/BUS_INTERFACE/ps_mbus' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/SPI_INTERFACE/ps_spi' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 INFO - synthesis: Extracted state machine for register '\Z_AXIS_MOTOR/CONFIGURATION_FIFO/data_bit_counter' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/StepperControl/sCurrentState' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 INFO - synthesis: Extracted state machine for register '\Z_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 INFO - synthesis: Extracted state machine for register '\Z_AXIS_MOTOR/SPI_INTERFACE/ps_spi' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/CONFIGURATION_FIFO/data_bit_counter' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 INFO - synthesis: Extracted state machine for register '\Z_AXIS_MOTOR/StepperControl/sCurrentState' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sCurrentState' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 INFO - synthesis: Extracted state machine for register '\Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sCurrentState' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 WARNING - synthesis: Bit 0 of Register \SENSORS/MEMORY/REGISTERS[2].REG/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 0 of Register \ERROR_LIST/ERROR_MEMORY/REGISTERS[1].REG/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 0 of Register \SENSORS/MEMORY/REGISTERS[0].REG/sys_bus_o.dat is stuck at Zero Removed duplicate sequential element \ERROR_LIST/LIMIT_MEMORY/REGISTERS[1].REG/p_data_out(8 bit), because it is equivalent to \PROTECTION_MASK/MEMORY/REGISTERS[1].REG/p_data_out Removed duplicate sequential element \ERROR_LIST/LIMIT_MEMORY/REGISTERS[2].REG/p_data_out(8 bit), because it is equivalent to \PROTECTION_MASK/MEMORY/REGISTERS[2].REG/p_data_out Removed duplicate sequential element \ERROR_LIST/LIMIT_MEMORY/REGISTERS[3].REG/p_data_out(8 bit), because it is equivalent to \PROTECTION_MASK/MEMORY/REGISTERS[3].REG/p_data_out Removed duplicate sequential element \ERROR_LIST/LIMIT_MEMORY/REGISTERS[4].REG/p_data_out(8 bit), because it is equivalent to \PROTECTION_MASK/MEMORY/REGISTERS[4].REG/p_data_out Removed duplicate sequential element \ERROR_LIST/LIMIT_MEMORY/REGISTERS[5].REG/p_data_out(8 bit), because it is equivalent to \PROTECTION_MASK/MEMORY/REGISTERS[5].REG/p_data_out Removed duplicate sequential element \ERROR_LIST/LIMIT_MEMORY/REGISTERS[6].REG/p_data_out(8 bit), because it is equivalent to \PROTECTION_MASK/MEMORY/REGISTERS[6].REG/p_data_out Removed duplicate sequential element \ERROR_LIST/LIMIT_MEMORY/REGISTERS[7].REG/p_data_out(8 bit), because it is equivalent to \PROTECTION_MASK/MEMORY/REGISTERS[7].REG/p_data_out Removed duplicate sequential element \ERROR_LIST/LIMIT_MEMORY/REGISTERS[0].REG/p_data_out(8 bit), because it is equivalent to \PROTECTION_MASK/MEMORY/REGISTERS[0].REG/p_data_out WARNING - synthesis: Bit 19 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 0 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero WARNING - synthesis: Bit 1 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero WARNING - synthesis: Bit 2 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero WARNING - synthesis: Bit 3 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero WARNING - synthesis: Bit 19 of Register \Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 0 of Register \Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero WARNING - synthesis: Bit 1 of Register \Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero WARNING - synthesis: Bit 2 of Register \Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero WARNING - synthesis: Bit 3 of Register \Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero WARNING - synthesis: Bit 0 of Register \X_AXIS_MOTOR/StepperControl/sMovementState is stuck at Zero WARNING - synthesis: Bit 0 of Register \Z_AXIS_MOTOR/StepperControl/sMovementState is stuck at Zero WARNING - synthesis: Bit 18 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 18 of Register \Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 17 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 17 of Register \Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 16 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 16 of Register \Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 15 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 15 of Register \Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 14 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero WARNING - synthesis: Bit 14 of Register \Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero ######## Pruned 1 high address bits on RAM Instance : \X_AXIS_MOTOR/STREAM_FIFO/clk_write_port_12 on net : \X_AXIS_MOTOR/STREAM_FIFO/memory ######## Pruned 1 high address bits on RAM Instance : \X_AXIS_MOTOR/STREAM_FIFO/rd_pointer_2__N_1673_2__I_0 on net : \X_AXIS_MOTOR/STREAM_FIFO/memory ######## Pruned 1 high address bits on RAM Instance : \Z_AXIS_MOTOR/STREAM_FIFO/rd_pointer_2__N_1673_2__I_0 on net : \Z_AXIS_MOTOR/STREAM_FIFO/memory ######## Pruned 1 high address bits on RAM Instance : \Z_AXIS_MOTOR/STREAM_FIFO/clk_write_port_12 on net : \Z_AXIS_MOTOR/STREAM_FIFO/memory Core reset RAM implemented for net n8542. Core reset RAM implemented for net n8543. ######## Found 2 RTL RAMs in the design. ######## Mapping RTL RAM n8542 to 6 Distributed blocks in PSEUDO_DUAL_PORT Mode ######## Mapping RTL RAM n8543 to 6 Distributed blocks in PSEUDO_DUAL_PORT Mode WARNING - synthesis: Register creset_3350 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3346 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3342 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3338 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3334 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3298 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3289 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3285 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3281 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3277 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3273 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3354 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3269 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3265 is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset is stuck at Zero. VDB-5013 WARNING - synthesis: Register creset_3358 is stuck at Zero. VDB-5013 WARNING - synthesis: Skipping pad insertion on IO_DATA[40] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[39] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[38] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[37] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[36] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[35] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[34] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[33] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[32] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[31] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[30] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[29] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[28] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[27] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[26] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[25] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[24] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[23] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[22] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[21] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[20] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[19] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[18] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[17] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[16] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[15] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[14] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[13] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[12] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[11] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[10] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[9] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[8] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[7] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[6] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[5] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[4] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[3] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[2] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[1] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[0] due to black_box_pad_pin attribute. WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd(273): Register \Z_AXIS_MOTOR/CONFIGURATION_FIFO/data_bit_counter_FSM_i24 is stuck at Zero. VDB-5013 Optimized async. reset : rst on data cone feeding flop : \Z_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i1 \Z_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i3 \Z_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i4 Optimized async. reset : rst on data cone feeding flop : \X_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i1 \X_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i3 \X_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i4 GSR instance connected to net n12076. Applying 54.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in TOP_LEVEL_drc.log. Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Running DRC... WARNING - synthesis: logical net 'port_in_async_11_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_14_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_15_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_16_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_18_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_19_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_20_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_21_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_22_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_24_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_25_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_26_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_27_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_28_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_30_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_31_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_32_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_33_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_34_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_36_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_37_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_38_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_39_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_40_.dat' has no load. WARNING - synthesis: DRC complete with 24 warnings. Design Results: 4552 blocks expanded completed the first expansion All blocks are expanded and NGD expansion is successful. Writing NGD file Project_impl1.ngd. ################### Begin Area Report (TOP_LEVEL)###################### Number of register bits => 1921 of 7209 (26 % ) BB => 41 CCU2D => 866 DPR16X4C => 12 FD1P3AX => 575 FD1P3AY => 16 FD1P3DX => 156 FD1P3IX => 464 FD1P3JX => 21 FD1S3AX => 116 FD1S3AY => 15 FD1S3DX => 102 FD1S3IX => 448 FD1S3JX => 8 GSR => 1 IB => 5 L6MUX21 => 2 LUT4 => 1628 MUX21 => 3 OB => 1 PFUMX => 53 ROM16X1A => 16 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : ClockFPGA_c, loads : 1933 Clock Enable Nets Number of Clock Enables: 237 Top 10 highest fanout Clock Enables: Net : SENSORS/X_SENSORS/ClockFPGA_c_enable_756, loads : 32 Net : SENSORS/Z_SENSORS/ClockFPGA_c_enable_548, loads : 32 Net : X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_303, loads : 27 Net : Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_119, loads : 27 Net : X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_791, loads : 24 Net : Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_652, loads : 24 Net : Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_776, loads : 24 Net : X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_783, loads : 24 Net : X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_394, loads : 23 Net : Z_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_327, loads : 23 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : Z_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_881, loads : 164 Net : n25591, loads : 84 Net : n25583, loads : 84 Net : SPI_BUS_COMMUNICATION/BUS_INTERFACE/master_bus_o.we, loads : 66 Net : Z_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_1624, loads : 57 Net : X_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_1624, loads : 55 Net : X_AXIS_MOTOR/n25600, loads : 46 Net : GPIO_MANAGEMENT/MEMORY/n25530, loads : 45 Net : Z_AXIS_MOTOR/StepperControl/n25481, loads : 43 Net : X_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_266, loads : 40 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 18.518519 -name | | | clk0 [get_nets ClockFPGA_c] | 54.001 MHz| 52.757 MHz| 13 * | | | -------------------------------------------------------------------------------- 1 constraints not met. Peak Memory Usage: 279.145 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 8.630 secs -------------------------------------------------------------- Nothing is executed for the "Translate" process map -a "MachXO2" -p LCMXO2-7000HC -t TQFP144 -s 4 -oc Commercial "Project_impl1.ngd" -o "Project_impl1_map.ncd" -pr "Project_impl1.prf" -mp "Project_impl1.mrp" -lpf "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/build/Project_impl1.lpf" -lpf "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/constraints.lpf" -c 0 map: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Process the file: Project_impl1.ngd Picdevice="LCMXO2-7000HC" Pictype="TQFP144" Picspeed=4 Remove unused logic Do not produce over sized NCDs. Part used: LCMXO2-7000HCTQFP144, Performance used: 4. Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Running general design DRC... Removing unused logic... Optimizing... Design Summary: Number of registers: 1921 out of 7209 (27%) PFU registers: 1921 out of 6864 (28%) PIO registers: 0 out of 345 (0%) Number of SLICEs: 1764 out of 3432 (51%) SLICEs as Logic/ROM: 1728 out of 3432 (50%) SLICEs as RAM: 36 out of 2574 (1%) SLICEs as Carry: 866 out of 3432 (25%) Number of LUT4s: 3455 out of 6864 (50%) Number used as logic LUTs: 1651 Number used as distributed RAM: 72 Number used as ripple logic: 1732 Number used as shift registers: 0 Number of PIO sites used: 47 + 4(JTAG) out of 115 (44%) Number of block RAMs: 0 out of 26 (0%) Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 2 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 1 Net ClockFPGA_c: 1187 loads, 1187 rising, 0 falling (Driver: PIO ClockFPGA ) Number of Clock Enables: 237 Net ClockFPGA_c_enable_227: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_228: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_229: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_230: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_231: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_121: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_137: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_143: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_178: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_232: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_203: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_206: 1 loads, 1 LSLICEs Net wr_pointer_2__N_1688: 3 loads, 3 LSLICEs Net ClockFPGA_c_enable_299: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_298: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_213: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_292: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_293: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_289: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_287: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_296: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_295: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_40: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_233: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_224: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_220: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_119: 12 loads, 12 LSLICEs Net ClockFPGA_c_enable_552: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_303: 12 loads, 12 LSLICEs Net ClockFPGA_c_enable_269: 2 loads, 2 LSLICEs Net GPIO_MANAGEMENT/MEMORY/ClockFPGA_c_enable_371: 4 loads, 4 LSLICEs Net GPIO_MANAGEMENT/MEMORY/ClockFPGA_c_enable_334: 4 loads, 4 LSLICEs Net shift_reg_3__N_787_adj_3726: 2 loads, 2 LSLICEs Net shift_reg_3__N_787_adj_3786: 2 loads, 2 LSLICEs Net rst: 90 loads, 90 LSLICEs Net shift_reg_3__N_787_adj_3773: 2 loads, 2 LSLICEs Net shift_reg_3__N_787_adj_3721: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_114: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_345: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_438: 1 loads, 1 LSLICEs Net Y_AXIS_MOTOR/ClockFPGA_c_enable_457: 4 loads, 4 LSLICEs Net Y_AXIS_MOTOR/ClockFPGA_c_enable_396: 1 loads, 1 LSLICEs Net p_data_out_7__N_2611: 4 loads, 4 LSLICEs Net p_data_out_7__N_2578: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_8: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_11: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_290: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_6: 1 loads, 1 LSLICEs Net ERROR_LIST/Z_MOTOR_ACTIVE/shift_reg_3__N_787: 2 loads, 2 LSLICEs Net ERROR_LIST/Z_ENCODER_DSP/ClockFPGA_c_enable_472: 9 loads, 9 LSLICEs Net ERROR_LIST/Y_MOTOR_ACTIVE/shift_reg_3__N_787: 2 loads, 2 LSLICEs Net ERROR_LIST/X_ENCODER_DSP/ClockFPGA_c_enable_361: 9 loads, 9 LSLICEs Net ERROR_LIST/STABILIZERS_4..DEBOUNCE/shift_reg_3__N_787: 2 loads, 2 LSLICEs Net shift_reg_3__N_787_adj_3780: 2 loads, 2 LSLICEs Net ERROR_LIST/STABILIZERS_1..DEBOUNCE/shift_reg_3__N_787: 2 loads, 2 LSLICEs Net ERROR_LIST/STABILIZERS_0..DEBOUNCE/shift_reg_3__N_787: 2 loads, 2 LSLICEs Net X_AXIS_MOTOR/spi_r_tvalid: 12 loads, 12 LSLICEs Net X_AXIS_MOTOR/ClockFPGA_c_enable_214: 2 loads, 2 LSLICEs Net X_AXIS_MOTOR/ClockFPGA_c_enable_590: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_266: 11 loads, 11 LSLICEs Net ClockFPGA_c_enable_115: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_807: 8 loads, 8 LSLICEs Net X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_885: 8 loads, 8 LSLICEs Net X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_783: 19 loads, 19 LSLICEs Net X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_619: 10 loads, 10 LSLICEs Net ClockFPGA_c_enable_634: 8 loads, 8 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_136: 2 loads, 2 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_150: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_151: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_152: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_155: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_156: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_157: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_159: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_160: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_161: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_162: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_163: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_164: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_791: 13 loads, 13 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_190: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_191: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_192: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_193: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_194: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_195: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_196: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_199: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_200: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_202: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_204: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_792: 1 loads, 1 LSLICEs Net p_data_out_7__N_2514: 4 loads, 4 LSLICEs Net X_AXIS_MOTOR/MEMORY/REGISTERS_4..REG/p_data_out_7__N_2481: 4 loads, 4 LSLICEs Net p_data_out_7__N_901: 4 loads, 4 LSLICEs Net p_data_out_7__N_2718: 4 loads, 4 LSLICEs Net p_data_out_7__N_374: 4 loads, 4 LSLICEs Net p_data_out_7__N_2448: 4 loads, 4 LSLICEs Net p_data_out_7__N_2415: 4 loads, 4 LSLICEs Net p_data_out_7__N_2382: 4 loads, 4 LSLICEs Net p_data_out_7__N_2349: 4 loads, 4 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_80: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_340: 3 loads, 3 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_210: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_394: 12 loads, 12 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_405: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_406: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_407: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_408: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_409: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_410: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_411: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_412: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_413: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_414: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_415: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_416: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_417: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_418: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_419: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_420: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_421: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_422: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_423: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_424: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_425: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_426: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_427: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/spi_r_tvalid: 12 loads, 12 LSLICEs Net Z_AXIS_MOTOR/ClockFPGA_c_enable_335: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/ClockFPGA_c_enable_122: 2 loads, 2 LSLICEs Net Z_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_221: 11 loads, 11 LSLICEs Net Z_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_434: 8 loads, 8 LSLICEs Net Z_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_130: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_131: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_686: 8 loads, 8 LSLICEs Net Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_887: 8 loads, 8 LSLICEs Net Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_652: 19 loads, 19 LSLICEs Net Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_671: 10 loads, 10 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_518: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_514: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_510: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_506: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_502: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_498: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_517: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_513: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_509: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_505: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_501: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_450: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_512: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_515: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_511: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_508: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_507: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_504: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_500: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_503: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_449: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_499: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_516: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_777: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_776: 13 loads, 13 LSLICEs Net Z_AXIS_MOTOR/MEMORY/p_data_out_7__N_2883: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/MEMORY/p_data_out_7__N_2850: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/MEMORY/REGISTERS_3..REG/p_data_out_7__N_2817: 4 loads, 4 LSLICEs Net p_data_out_7__N_2985: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/MEMORY/p_data_out_7__N_2784: 4 loads, 4 LSLICEs Net p_data_out_7__N_2751: 4 loads, 4 LSLICEs Net p_data_out_7__N_967: 4 loads, 4 LSLICEs Net ClockFPGA_c_enable_127: 3 loads, 3 LSLICEs Net ClockFPGA_c_enable_111: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_149: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_225: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_226: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_234: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_235: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_236: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_237: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_238: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_239: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_240: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_241: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_242: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_243: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_244: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_245: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_246: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_247: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_327: 12 loads, 12 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_211: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_402: 4 loads, 4 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_404: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_12: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_13: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_15: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_16: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_442: 3 loads, 3 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_710: 3 loads, 3 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_775: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_445: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_444: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_443: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_439: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_437: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_436: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_435: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_448: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_447: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_446: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/BUS_INTERFACE/ClockFPGA_c_enable_223: 5 loads, 5 LSLICEs Net ClockFPGA_c_enable_364: 2 loads, 2 LSLICEs Net ClockFPGA_c_enable_473: 2 loads, 2 LSLICEs Net Z_ENCODER/ClockFPGA_c_enable_725: 9 loads, 9 LSLICEs Net ENVIRONMENT_GREEN/blink_counter_enb: 4 loads, 4 LSLICEs Net p_data_out_7__N_3393: 4 loads, 4 LSLICEs Net p_data_out_7__N_934: 4 loads, 4 LSLICEs Net p_data_out_7__N_3291: 4 loads, 4 LSLICEs Net p_data_out_7__N_3189: 4 loads, 4 LSLICEs Net p_data_out_7__N_3087: 4 loads, 4 LSLICEs Net shift_reg_3__N_787: 2 loads, 2 LSLICEs Net SENSORS/Z_SENSORS/ClockFPGA_c_enable_548: 17 loads, 17 LSLICEs Net SENSORS/X_SENSORS/ClockFPGA_c_enable_756: 17 loads, 17 LSLICEs Net ENVIRONMENT_RED/blink_counter_enb: 4 loads, 4 LSLICEs Net POWER_GREEN/blink_counter_enb: 4 loads, 4 LSLICEs Net ENVIRONMENT_WHITE/blink_counter_enb: 4 loads, 4 LSLICEs Net PROTECTION_MASK/STABILIZERS_4..DEBOUNCE/shift_reg_3__N_787: 2 loads, 2 LSLICEs Net PROTECTION_MASK/STABILIZERS_2..DEBOUNCE/shift_reg_3__N_787: 2 loads, 2 LSLICEs Net PROTECTION_MASK/STABILIZERS_1..DEBOUNCE/shift_reg_3__N_787: 2 loads, 2 LSLICEs Net PROTECTION_MASK/MEMORY/REGISTERS_7..REG/p_data_out_7__N_1132: 4 loads, 4 LSLICEs Net PROTECTION_MASK/MEMORY/p_data_out_7__N_1000: 4 loads, 4 LSLICEs Net PROTECTION_MASK/MEMORY/p_data_out_7__N_1099: 4 loads, 4 LSLICEs Net PROTECTION_MASK/MEMORY/REGISTERS_5..REG/p_data_out_7__N_1066: 4 loads, 4 LSLICEs Net PROTECTION_MASK/MEMORY/p_data_out_7__N_1033: 4 loads, 4 LSLICEs Net POWER_RED/blink_counter_enb: 4 loads, 4 LSLICEs Net X_ENCODER/ClockFPGA_c_enable_771: 9 loads, 9 LSLICEs Number of LSRs: 101 Net n2891: 1 loads, 1 LSLICEs Net n19336: 3 loads, 3 LSLICEs Net n25600: 28 loads, 28 LSLICEs Net n13002: 7 loads, 7 LSLICEs Net n2630: 1 loads, 1 LSLICEs Net n12779: 3 loads, 3 LSLICEs Net n12989: 7 loads, 7 LSLICEs Net n25481: 30 loads, 30 LSLICEs Net miso_buffer_i_23__N_1888_adj_3969: 1 loads, 1 LSLICEs Net miso_buffer_i_23__N_1888: 1 loads, 1 LSLICEs Net GPIO_MANAGEMENT/MEMORY/sys_bus_o.dat_7__N_1473: 5 loads, 5 LSLICEs Net n17842: 6 loads, 6 LSLICEs Net n17745: 6 loads, 6 LSLICEs Net n25552: 16 loads, 16 LSLICEs Net Y_AXIS_MOTOR/n3343: 3 loads, 3 LSLICEs Net Y_AXIS_MOTOR/n3346: 5 loads, 5 LSLICEs Net n12783: 4 loads, 4 LSLICEs Net n12818: 4 loads, 4 LSLICEs Net n25547: 13 loads, 13 LSLICEs Net ERROR_LIST/Z_MOTOR_ACTIVE/n12829: 6 loads, 6 LSLICEs Net n25583: 54 loads, 54 LSLICEs Net ERROR_LIST/Y_MOTOR_ACTIVE/n12828: 6 loads, 6 LSLICEs Net n17579: 6 loads, 6 LSLICEs Net n25591: 54 loads, 54 LSLICEs Net n17647: 6 loads, 6 LSLICEs Net ERROR_LIST/STABILIZERS_4..DEBOUNCE/n12778: 6 loads, 6 LSLICEs Net n17830: 6 loads, 6 LSLICEs Net ERROR_LIST/STABILIZERS_1..DEBOUNCE/n12770: 6 loads, 6 LSLICEs Net n14499: 6 loads, 6 LSLICEs Net n12732: 7 loads, 7 LSLICEs Net n12793: 8 loads, 8 LSLICEs Net X_AXIS_MOTOR/p_tdword_tready_N_1912: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/sStopMovement: 5 loads, 5 LSLICEs Net X_AXIS_MOTOR/sCurrentState_2_N_1535_1: 1 loads, 1 LSLICEs Net X_AXIS_MOTOR/StepperControl/n3473: 4 loads, 4 LSLICEs Net X_AXIS_MOTOR/StepperControl/sCounter1us_5__N_1976: 11 loads, 11 LSLICEs Net n13806: 8 loads, 8 LSLICEs Net X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/n8226: 16 loads, 16 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/n7937: 4 loads, 4 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/n3470: 3 loads, 3 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/n25470: 3 loads, 3 LSLICEs Net X_AXIS_MOTOR/SPI_INTERFACE/n12744: 1 loads, 1 LSLICEs Net n12782: 4 loads, 4 LSLICEs Net X_AXIS_MOTOR/MEMORY/REGISTERS_4..REG/n12781: 4 loads, 4 LSLICEs Net n12792: 4 loads, 4 LSLICEs Net n12819: 4 loads, 4 LSLICEs Net n12708: 4 loads, 4 LSLICEs Net n12780: 4 loads, 4 LSLICEs Net n12706: 4 loads, 4 LSLICEs Net n12784: 4 loads, 4 LSLICEs Net n12817: 4 loads, 4 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/n3452: 4 loads, 4 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_1622: 24 loads, 24 LSLICEs Net X_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_1623: 18 loads, 18 LSLICEs Net Z_AXIS_MOTOR/sCurrentState_2_N_2649_1: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/p_tdword_tready_N_1912: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/sStopMovement: 5 loads, 5 LSLICEs Net Z_AXIS_MOTOR/StepperControl/n3512: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/StepperControl/sCounter1us_5__N_1976: 11 loads, 11 LSLICEs Net Z_AXIS_MOTOR/StepperControl/n12920: 8 loads, 8 LSLICEs Net Z_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/n8249: 16 loads, 16 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/n7939: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/n3509: 3 loads, 3 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/n25469: 3 loads, 3 LSLICEs Net Z_AXIS_MOTOR/SPI_INTERFACE/n12759: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/MEMORY/n12789: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/MEMORY/n12787: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/MEMORY/REGISTERS_3..REG/n12786: 4 loads, 4 LSLICEs Net n12742: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/MEMORY/n12785: 4 loads, 4 LSLICEs Net n12712: 4 loads, 4 LSLICEs Net n12769: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_1623: 18 loads, 18 LSLICEs Net Z_AXIS_MOTOR/CONFIGURATION_FIFO/n3491: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_1622: 24 loads, 24 LSLICEs Net SPI_BUS_COMMUNICATION/p_master_bus_o.adr_9__N_335: 10 loads, 10 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/n10206: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/n10199: 1 loads, 1 LSLICEs Net ENVIRONMENT_GREEN/led_counter_21__N_3355: 12 loads, 12 LSLICEs Net n12768: 4 loads, 4 LSLICEs Net n12764: 4 loads, 4 LSLICEs Net n12763: 4 loads, 4 LSLICEs Net n12762: 4 loads, 4 LSLICEs Net n12761: 4 loads, 4 LSLICEs Net SENSORS/MEMORY/n12765: 4 loads, 4 LSLICEs Net SENSORS/MEMORY/REGISTERS_2..REG/n12766: 4 loads, 4 LSLICEs Net SENSORS/MEMORY/n12790: 4 loads, 4 LSLICEs Net ENVIRONMENT_RED/led_counter_21__N_3151: 12 loads, 12 LSLICEs Net POWER_GREEN/led_counter_21__N_3049: 12 loads, 12 LSLICEs Net ENVIRONMENT_WHITE/led_counter_21__N_3253: 12 loads, 12 LSLICEs Net PROTECTION_MASK/STABILIZERS_5..DEBOUNCE/n12713: 6 loads, 6 LSLICEs Net PROTECTION_MASK/STABILIZERS_4..DEBOUNCE/n12745: 6 loads, 6 LSLICEs Net PROTECTION_MASK/STABILIZERS_2..DEBOUNCE/n12709: 6 loads, 6 LSLICEs Net PROTECTION_MASK/STABILIZERS_1..DEBOUNCE/n12826: 6 loads, 6 LSLICEs Net PROTECTION_MASK/STABILIZERS_0..DEBOUNCE/n12825: 6 loads, 6 LSLICEs Net PROTECTION_MASK/MEMORY/REGISTERS_7..REG/n12776: 4 loads, 4 LSLICEs Net PROTECTION_MASK/MEMORY/n12771: 4 loads, 4 LSLICEs Net PROTECTION_MASK/MEMORY/n12775: 4 loads, 4 LSLICEs Net PROTECTION_MASK/MEMORY/REGISTERS_5..REG/n12774: 4 loads, 4 LSLICEs Net PROTECTION_MASK/MEMORY/n12772: 4 loads, 4 LSLICEs Net POWER_RED/led_counter_21__N_2947: 12 loads, 12 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net rst: 126 loads Net master_bus_o.we: 68 loads Net p_cword_tdata_23__N_1624_adj_3934: 59 loads Net p_cword_tdata_23__N_1624: 57 loads Net n25583: 54 loads Net n25591: 54 loads Net rd_pointer_2_N_1673_2: 48 loads Net rd_pointer_2_N_1673_2_adj_3941: 48 loads Net n25530: 47 loads Net X_AXIS_MOTOR/p_tdword_tready_N_1912: 34 loads Number of warnings: 0 Number of errors: 0 Total CPU Time: 2 secs Total REAL Time: 3 secs Peak Memory Usage: 209 MB Dumping design to file Project_impl1_map.ncd. ncd2vdb "Project_impl1_map.ncd" ".vdbs/Project_impl1_map.vdb" Loading device for application ncd2vdb from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. mpartrce -p "Project_impl1.p2t" -f "Project_impl1.p3t" -tf "Project_impl1.pt" "Project_impl1_map.ncd" "Project_impl1.ncd" ---- MParTrce Tool ---- Removing old design directory at request of -rem command line option to this program. Running par. Please wait . . . Lattice Place and Route Report for Design "Project_impl1_map.ncd" Tue Aug 27 09:31:25 2024 PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 Project_impl1_map.ncd Project_impl1.dir/5_1.ncd Project_impl1.prf Preference file: Project_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file Project_impl1_map.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 47+4(JTAG)/336 15% used 47+4(JTAG)/115 44% bonded SLICE 1764/3432 51% used GSR 1/1 100% used Number of Signals: 5123 Number of Connections: 13526 Pin Constraint Summary: 47 out of 47 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: ClockFPGA_c (driver: ClockFPGA, clk load #: 1187) The following 8 signals are selected to use the secondary clock routing resources: rst (driver: SLICE_754, clk load #: 0, sr load #: 0, ce load #: 90) n25583 (driver: SLICE_2293, clk load #: 0, sr load #: 54, ce load #: 0) n25591 (driver: SLICE_2294, clk load #: 0, sr load #: 54, ce load #: 0) n25481 (driver: Z_AXIS_MOTOR/SLICE_1294, clk load #: 0, sr load #: 30, ce load #: 0) n25600 (driver: X_AXIS_MOTOR/SLICE_2252, clk load #: 0, sr load #: 28, ce load #: 0) X_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_1622 (driver: X_AXIS_MOTOR/CONFIGURATION_FIFO/SLICE_1058, clk load #: 0, sr load #: 24, ce load #: 0) Z_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_1622 (driver: SLICE_1827, clk load #: 0, sr load #: 24, ce load #: 0) X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_783 (driver: SLICE_2305, clk load #: 0, sr load #: 0, ce load #: 19) Signal rst is selected as Global Set/Reset. Starting Placer Phase 0. .......... Finished Placer Phase 0. REAL time: 3 secs Starting Placer Phase 1. ......................... Placer score = 921941. Finished Placer Phase 1. REAL time: 17 secs Starting Placer Phase 2. . Placer score = 914124 Finished Placer Phase 2. REAL time: 18 secs ------------------ Clock Report ------------------ Global Clock Resources: CLK_PIN : 1 out of 8 (12%) PLL : 0 out of 2 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: PRIMARY "ClockFPGA_c" from comp "ClockFPGA" on CLK_PIN site "128 (PT18A)", clk load = 1187 SECONDARY "rst" from Q1 on comp "SLICE_754" on site "R19C20C", clk load = 0, ce load = 90, sr load = 0 SECONDARY "n25583" from F0 on comp "SLICE_2293" on site "R14C18C", clk load = 0, ce load = 0, sr load = 54 SECONDARY "n25591" from F0 on comp "SLICE_2294" on site "R21C18D", clk load = 0, ce load = 0, sr load = 54 SECONDARY "n25481" from F1 on comp "Z_AXIS_MOTOR/SLICE_1294" on site "R14C20C", clk load = 0, ce load = 0, sr load = 30 SECONDARY "n25600" from F0 on comp "X_AXIS_MOTOR/SLICE_2252" on site "R14C20D", clk load = 0, ce load = 0, sr load = 28 SECONDARY "X_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_1622" from F1 on comp "X_AXIS_MOTOR/CONFIGURATION_FIFO/SLICE_1058" on site "R14C20A", clk load = 0, ce load = 0, sr load = 24 SECONDARY "Z_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_1622" from F1 on comp "SLICE_1827" on site "R14C20B", clk load = 0, ce load = 0, sr load = 24 SECONDARY "X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_783" from F0 on comp "SLICE_2305" on site "R14C21D", clk load = 0, ce load = 19, sr load = 0 PRIMARY : 1 out of 8 (12%) SECONDARY: 8 out of 8 (100%) Edge Clocks: No edge clock selected. --------------- End of Clock Report --------------- I/O Usage Summary (final): 47 + 4(JTAG) out of 336 (15.2%) PIO sites used. 47 + 4(JTAG) out of 115 (44.3%) bonded PIO sites used. Number of PIO comps: 47; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ | 0 | 10 / 28 ( 35%) | 3.3V | - | | 1 | 28 / 29 ( 96%) | 3.3V | - | | 2 | 1 / 29 ( 3%) | 3.3V | - | | 3 | 3 / 9 ( 33%) | 3.3V | - | | 4 | 2 / 10 ( 20%) | 3.3V | - | | 5 | 3 / 10 ( 30%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 17 secs Dumping design to file Project_impl1.dir/5_1.ncd. 0 connections routed; 13526 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 20 secs Start NBR router at Tue Aug 27 09:31:46 UTC 2024 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at Tue Aug 27 09:31:46 UTC 2024 Start NBR section for initial routing at Tue Aug 27 09:31:46 UTC 2024 Level 1, iteration 1 1(0.00%) conflict; 10012(74.02%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.805ns/0.000ns; real time: 21 secs Level 2, iteration 1 5(0.00%) conflicts; 9998(73.92%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 2.529ns/0.000ns; real time: 21 secs Level 3, iteration 1 5(0.00%) conflicts; 9734(71.97%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 2.278ns/0.000ns; real time: 22 secs Level 4, iteration 1 445(0.12%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.837ns/0.000ns; real time: 23 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 23 (2.30%) Start NBR section for normal routing at Tue Aug 27 09:31:49 UTC 2024 Level 1, iteration 1 1(0.00%) conflict; 563(4.16%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.837ns/0.000ns; real time: 24 secs Level 2, iteration 1 0(0.00%) conflict; 565(4.18%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.837ns/0.000ns; real time: 24 secs Level 3, iteration 1 0(0.00%) conflict; 565(4.18%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 1.837ns/0.000ns; real time: 24 secs Level 4, iteration 1 244(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.255ns/0.000ns; real time: 24 secs Level 4, iteration 2 124(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.255ns/0.000ns; real time: 25 secs Level 4, iteration 3 66(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.319ns/0.000ns; real time: 25 secs Level 4, iteration 4 36(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 1.319ns/0.000ns; real time: 25 secs Level 4, iteration 5 20(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.219ns/0.000ns; real time: 25 secs Level 4, iteration 6 22(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.219ns/0.000ns; real time: 25 secs Level 4, iteration 7 13(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.219ns/0.000ns; real time: 26 secs Level 4, iteration 8 6(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.219ns/0.000ns; real time: 26 secs Level 4, iteration 9 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.219ns/0.000ns; real time: 26 secs Level 4, iteration 10 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.219ns/0.000ns; real time: 26 secs Level 4, iteration 11 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.219ns/0.000ns; real time: 26 secs Start NBR section for setup/hold timing optimization with effort level 3 at Tue Aug 27 09:31:51 UTC 2024 Start NBR section for re-routing at Tue Aug 27 09:31:52 UTC 2024 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 2.219ns/0.000ns; real time: 27 secs Start NBR section for post-routing at Tue Aug 27 09:31:52 UTC 2024 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack : 2.219ns Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 28 secs Total REAL time: 28 secs Completely routed. End of route. 13526 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file Project_impl1.dir/5_1.ncd. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack> = 2.219 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Worst slack> = 0.137 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 28 secs Total REAL time to completion: 29 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Exiting par with exit code 0 Exiting mpartrce with exit code 0 trce -f "Project_impl1.pt" -o "Project_impl1.twr" "Project_impl1.ncd" "Project_impl1.prf" trce: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application trce from file Project_impl1.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 Tue Aug 27 09:31:56 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Project_impl1.twr Project_impl1.ncd Project_impl1.prf Design file: Project_impl1.ncd Preference file: Project_impl1.prf Device,speed: LCMXO2-7000HC,4 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 68290 paths, 1 nets, and 13431 connections (99.30% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 Tue Aug 27 09:31:56 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Project_impl1.twr Project_impl1.ncd Project_impl1.prf Design file: Project_impl1.ncd Preference file: Project_impl1.prf Device,speed: LCMXO2-7000HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 68290 paths, 1 nets, and 13431 connections (99.30% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Total CPU Time: 1 secs Total REAL Time: 0 secs Peak Memory Usage: 175 MB Nothing is executed for the "PAR - PARTrace" process tmcheck -par "Project_impl1.par" bitgen -f "Project_impl1.t2b" -w "Project_impl1.ncd" "Project_impl1.prf" BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application Bitgen from file Project_impl1.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Running DRC. DRC detected 0 errors and 0 warnings. Reading Preference File from Project_impl1.prf. Preference Summary: +---------------------------------+---------------------------------+ | Preference | Current Setting | +---------------------------------+---------------------------------+ | RamCfg | Reset** | +---------------------------------+---------------------------------+ | MCCLK_FREQ | 2.08** | +---------------------------------+---------------------------------+ | CONFIG_SECURE | OFF** | +---------------------------------+---------------------------------+ | INBUF | ON** | +---------------------------------+---------------------------------+ | JTAG_PORT | ENABLE** | +---------------------------------+---------------------------------+ | SDM_PORT | DISABLE** | +---------------------------------+---------------------------------+ | SLAVE_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MASTER_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | I2C_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MUX_CONFIGURATION_PORTS | DISABLE** | +---------------------------------+---------------------------------+ | CONFIGURATION | CFG** | +---------------------------------+---------------------------------+ | COMPRESS_CONFIG | ON** | +---------------------------------+---------------------------------+ | MY_ASSP | OFF** | +---------------------------------+---------------------------------+ | ONE_TIME_PROGRAM | OFF** | +---------------------------------+---------------------------------+ | ENABLE_TRANSFR | DISABLE** | +---------------------------------+---------------------------------+ | SHAREDEBRINIT | DISABLE** | +---------------------------------+---------------------------------+ | BACKGROUND_RECONFIG | OFF** | +---------------------------------+---------------------------------+ * Default setting. ** The specified setting matches the default setting. Creating bit map... Bitstream Status: Final Version 1.95. Saving bit stream in "Project_impl1.bit". Total CPU Time: 3 secs Total REAL Time: 3 secs Peak Memory Usage: 437 MB RTNETLINK answers: File exists Lattice Diamond Deployment Tool 3.12 Command Line Loading Programmer Device Database... Generating SVF..... Reading Input File: build/Project_impl1.bit Output File: dist/bitstream.svf Generate Single SVF file: Start Device 1 LCMXO2-7000HC:SRAM Erase,Program,Verify Build SVF File Operation: Successful. Lattice Diamond Deployment Tool has exited successfully.