RTNETLINK answers: File exists synthesis -f "Project_impl1_lattice.synproj" synthesis: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Mon Jun 2 07:46:43 2025 Command Line: synthesis -f Project_impl1_lattice.synproj INFO - synthesis: Lattice Synthesis Engine Launched. Synthesis options: The -a option is MachXO2. The -s option is 4. The -t option is TQFP144. The -d option is LCMXO2-7000HC. Using package TQFP144. Using performance grade 4. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-7000HC ### Package : TQFP144 ### Speed : 4 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = top_level. Target frequency = 54.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /usr/local/diamond/3.12/ispfpga/xo2c00/data (searchpath added) -p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/build (searchpath added) -p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga (searchpath added) VHDL library = work VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK_D.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/WH_SENSOR_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/GOLDI_MODULE_CONFIG.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR_D.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_CROSSBAR_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_R_DRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_D_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_TX_SDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_RX_SDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_STD_ENCODER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_S_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_TX_DDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_STD_DECODER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/uart/UART_RX_DDRIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_T_CONTROLLER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_R_CONTROLLER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_C_DIVER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/i2c/I2C_C_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/PWM_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/LED_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE_ENCODER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/StepperControl.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/EMAGNET_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_TABLE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_UNIT.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/STREAM_FIFO.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_UNIT.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_T_TABLE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/IO_CROSSBAR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/LOW_DEBOUNCE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/EDGE_DETECTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/CLOCK_DIVIDER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER.vhd NGD file = Project_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. -vh2008 Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file /usr/local/diamond/3.12/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin INFO - synthesis: The default VHDL library search path is now "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/build". VHDL-1504 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(5): analyzing package goldi_comm_standard. VHDL-1014 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(197): analyzing package body goldi_comm_standard. VHDL-1013 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd(5): analyzing package goldi_io_standard. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd(5): analyzing package goldi_data_types. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/GOLDI_MODULE_CONFIG.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/GOLDI_MODULE_CONFIG.vhd(11): analyzing package goldi_module_config. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd(12): analyzing entity high_debounce. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd(28): analyzing architecture bh. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_UNIT.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_UNIT.vhd(32): analyzing entity register_unit. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_UNIT.vhd(53): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_TABLE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_TABLE.vhd(42): analyzing entity register_table. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_TABLE.vhd(64): analyzing architecture bh. VHDL-1010 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/REGISTER_TABLE.vhd(143): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK_D.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK_D.vhd(47): analyzing entity actuator_mask_d. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK_D.vhd(74): analyzing architecture rtl. VHDL-1010 WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK_D.vhd(144): 'encoder_driver' is not compiled in library work. VHDL-1240 WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK_D.vhd(157): 'encoder_driver' is not compiled in library work. VHDL-1240 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR.vhd(16): analyzing entity error_detector. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR.vhd(43): analyzing architecture rtl. VHDL-1010 WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR.vhd(155): 'virtual_sensor_array' is not compiled in library work. VHDL-1240 WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR.vhd(170): 'virtual_sensor_array' is not compiled in library work. VHDL-1240 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/WH_SENSOR_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/WH_SENSOR_ARRAY.vhd(36): analyzing entity wh_sensor_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/WH_SENSOR_ARRAY.vhd(73): analyzing architecture rtl. VHDL-1010 WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/WH_SENSOR_ARRAY.vhd(107): 'virtual_sensor_array' is not compiled in library work. VHDL-1240 WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/WH_SENSOR_ARRAY.vhd(128): 'virtual_sensor_array' is not compiled in library work. VHDL-1240 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK.vhd(15): analyzing entity actuator_mask. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK.vhd(44): analyzing architecture rtl. VHDL-1010 WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK.vhd(108): 'virtual_sensor_array' is not compiled in library work. VHDL-1240 WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ACTUATOR_MASK.vhd(123): 'virtual_limit_array' is not compiled in library work. VHDL-1240 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR_D.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR_D.vhd(26): analyzing entity error_detector_d. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR_D.vhd(52): analyzing architecture rtl. VHDL-1010 WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR_D.vhd(169): 'encoder_driver' is not compiled in library work. VHDL-1240 WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/ERROR_DETECTOR_D.vhd(182): 'encoder_driver' is not compiled in library work. VHDL-1240 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd(10): analyzing entity synchronizer. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd(23): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(18): analyzing entity sp_converter. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(39): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(42): analyzing entity bus_adaptor. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(60): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(42): analyzing entity goldi_spi_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(59): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd(15): analyzing entity tris_buffer. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd(30): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(10): analyzing entity tris_buffer_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(28): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER.vhd(38): analyzing entity encoder. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER.vhd(56): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd(20): analyzing entity encoder_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd(39): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd(25): analyzing entity gpio_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd(44): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/CLOCK_DIVIDER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/CLOCK_DIVIDER.vhd(5): analyzing entity clock_divider. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/dsp/CLOCK_DIVIDER.vhd(16): analyzing architecture bhv. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd(32): analyzing entity rom16xn_fifo. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd(52): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd(43): analyzing entity spi_t_driver. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd(71): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/StepperControl.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/StepperControl.vhd(19): analyzing entity steppercontrol. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/StepperControl.vhd(35): analyzing architecture behavioral. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd(47): analyzing entity tmc2660_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd(80): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd(38): analyzing entity hbridge_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd(58): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/LED_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/LED_SMODULE.vhd(35): analyzing entity led_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/common/actuation/LED_SMODULE.vhd(54): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd(21): analyzing entity top_level. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd(41): analyzing architecture rtl. VHDL-1010 ERROR - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/warehouse_v2/fpga/src/TOP_LEVEL.vhd(344): formal g_index_rst is not declared. VHDL-1084 Running milestone "Synthesis" failed while executing "prj_run Synthesis -impl impl1" (file "project.tcl" line 2)