synthesis -f "Project_impl1_lattice.synproj" synthesis: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Tue Jun 18 13:33:41 2024 Command Line: synthesis -f Project_impl1_lattice.synproj INFO - synthesis: Lattice Synthesis Engine Launched. Synthesis options: The -a option is MachXO2. The -s option is 4. The -t option is TQFP144. The -d option is LCMXO2-7000HC. Using package TQFP144. Using performance grade 4. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-7000HC ### Package : TQFP144 ### Speed : 4 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = TOP_LEVEL. Target frequency = 54.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /usr/local/diamond/3.12/ispfpga/xo2c00/data (searchpath added) -p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/build (searchpath added) -p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga (searchpath added) VHDL library = work VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/TOP_LEVEL.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/GOLDI_MODULE_CONFIG.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/ACTUATOR_MASK.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/ERROR_DETECTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/GPIO_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/EMAGNET_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/LED_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/dsp/EDGE_DETECTOR.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/dsp/ENCODER_SMODULE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/SYNCHRONIZER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/TRIS_BUFFER.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/memory/REGISTER_TABLE.vhd VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/memory/REGISTER_UNIT.vhd NGD file = Project_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. -vh2008 Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file /usr/local/diamond/3.12/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin INFO - synthesis: The default VHDL library search path is now "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/build". VHDL-1504 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(39): analyzing package goldi_comm_standard. VHDL-1014 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(255): analyzing package body goldi_comm_standard. VHDL-1013 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd(32): analyzing package goldi_io_standard. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/GOLDI_MODULE_CONFIG.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/GOLDI_MODULE_CONFIG.vhd(33): analyzing package goldi_module_config. VHDL-1014 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/SYNCHRONIZER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/SYNCHRONIZER.vhd(38): analyzing entity synchronizer. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/SYNCHRONIZER.vhd(54): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(47): analyzing entity sp_converter. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(71): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(75): analyzing entity bus_adaptor. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(96): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(77): analyzing entity goldi_spi_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(97): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/memory/REGISTER_UNIT.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/memory/REGISTER_UNIT.vhd(63): analyzing entity register_unit. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/memory/REGISTER_UNIT.vhd(87): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/TRIS_BUFFER.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/TRIS_BUFFER.vhd(42): analyzing entity tris_buffer. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/TRIS_BUFFER.vhd(60): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(42): analyzing entity tris_buffer_array. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(63): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/dsp/EDGE_DETECTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/dsp/EDGE_DETECTOR.vhd(40): analyzing entity edge_detector. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/dsp/EDGE_DETECTOR.vhd(56): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/memory/REGISTER_TABLE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/memory/REGISTER_TABLE.vhd(82): analyzing entity register_table. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/memory/REGISTER_TABLE.vhd(107): analyzing architecture bh. VHDL-1010 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/memory/REGISTER_TABLE.vhd(196): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/ERROR_DETECTOR.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/ERROR_DETECTOR.vhd(46): analyzing entity error_detector. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/ERROR_DETECTOR.vhd(67): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/ACTUATOR_MASK.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/ACTUATOR_MASK.vhd(44): analyzing entity actuator_mask. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/ACTUATOR_MASK.vhd(58): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/dsp/ENCODER_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/dsp/ENCODER_SMODULE.vhd(89): analyzing entity encoder_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/dsp/ENCODER_SMODULE.vhd(113): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/GPIO_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/GPIO_SMODULE.vhd(60): analyzing entity gpio_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/GPIO_SMODULE.vhd(82): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd(71): analyzing entity hbridge_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd(94): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/EMAGNET_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/EMAGNET_SMODULE.vhd(59): analyzing entity emagnet_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/EMAGNET_SMODULE.vhd(83): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/LED_SMODULE.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/LED_SMODULE.vhd(71): analyzing entity led_smodule. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/actuation/LED_SMODULE.vhd(93): analyzing architecture rtl. VHDL-1010 Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/TOP_LEVEL.vhd. VHDL-1481 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/TOP_LEVEL.vhd(54): analyzing entity top_level. VHDL-1012 INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/TOP_LEVEL.vhd(74): analyzing architecture rtl. VHDL-1010 unit TOP_LEVEL is not yet analyzed. VHDL-1485 /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/TOP_LEVEL.vhd(54): executing TOP_LEVEL(RTL) WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/TOP_LEVEL.vhd(68): replacing existing netlist TOP_LEVEL(RTL). VHDL-1205 Top module name (VHDL): TOP_LEVEL Last elaborated design is TOP_LEVEL(RTL) Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Top-level module name = TOP_LEVEL. WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/src/common/dsp/ENCODER_SMODULE.vhd(197): Register \X_ENCODER/enc_block_37 is stuck at Zero. VDB-5013 INFO - synthesis: Extracted state machine for register '\CLAW_MAGNET/PS' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 INFO - synthesis: Extracted state machine for register '\SPI_BUS_COMMUNICATION/BUS_INTERFACE/ps_mbus' with one-hot encoding original encoding -> new encoding (one-hot encoding) 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 WARNING - synthesis: Bit 0 of Register \ERROR_LIST/MEMORY/REGISTERS[2].REG/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 0 of Register \SENSOR_REGISTER/REGISTERS[0].REG/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 1 of Register \SENSOR_REGISTER/REGISTERS[0].REG/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 2 of Register \SENSOR_REGISTER/REGISTERS[0].REG/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 3 of Register \SENSOR_REGISTER/REGISTERS[0].REG/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 4 of Register \SENSOR_REGISTER/REGISTERS[0].REG/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 5 of Register \SENSOR_REGISTER/REGISTERS[0].REG/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Bit 6 of Register \SENSOR_REGISTER/REGISTERS[0].REG/sys_bus_o.dat is stuck at Zero WARNING - synthesis: Skipping pad insertion on IO_DATA[40] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[39] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[38] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[37] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[36] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[35] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[34] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[33] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[32] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[31] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[30] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[29] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[28] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[27] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[26] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[25] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[24] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[23] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[22] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[21] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[20] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[19] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[18] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[17] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[16] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[15] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[14] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[13] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[12] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[11] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[10] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[9] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[8] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[7] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[6] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[5] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[4] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[3] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[2] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[1] due to black_box_pad_pin attribute. WARNING - synthesis: Skipping pad insertion on IO_DATA[0] due to black_box_pad_pin attribute. GSR instance connected to net n4329. Applying 54.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in TOP_LEVEL_drc.log. Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Running DRC... WARNING - synthesis: logical net 'port_in_async_13_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_16_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_17_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_18_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_19_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_20_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_21_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_22_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_23_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_24_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_25_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_26_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_27_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_28_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_29_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_30_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_31_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_32_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_33_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_34_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_35_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_36_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_37_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_38_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_39_.dat' has no load. WARNING - synthesis: logical net 'port_in_async_40_.dat' has no load. WARNING - synthesis: DRC complete with 26 warnings. Design Results: 1484 blocks expanded completed the first expansion All blocks are expanded and NGD expansion is successful. Writing NGD file Project_impl1.ngd. ################### Begin Area Report (TOP_LEVEL)###################### Number of register bits => 672 of 7209 (9 % ) BB => 41 CCU2D => 99 FD1P3AX => 146 FD1P3AY => 4 FD1P3DX => 32 FD1P3IX => 78 FD1P3JX => 3 FD1S3AX => 75 FD1S3AY => 8 FD1S3DX => 42 FD1S3IX => 282 FD1S3JX => 2 GSR => 1 IB => 5 L6MUX21 => 9 LUT4 => 609 OB => 1 PFUMX => 44 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : ClockFPGA_c, loads : 672 Clock Enable Nets Number of Clock Enables: 58 Top 10 highest fanout Clock Enables: Net : X_ENCODER/ClockFPGA_c_enable_80, loads : 16 Net : Y_ENCODER/ClockFPGA_c_enable_95, loads : 16 Net : SPI_BUS_COMMUNICATION/BUS_INTERFACE/ClockFPGA_c_enable_127, loads : 10 Net : Z_AXIS_MOTOR/ClockFPGA_c_enable_39, loads : 9 Net : X_AXIS_MOTOR/ClockFPGA_c_enable_53, loads : 9 Net : Y_AXIS_MOTOR/ClockFPGA_c_enable_46, loads : 9 Net : POWER_RED/blink_counter_enb, loads : 8 Net : GPIO_MANAGEMENT/MEMORY/ClockFPGA_c_enable_17, loads : 8 Net : GPIO_MANAGEMENT/MEMORY/ClockFPGA_c_enable_26, loads : 8 Net : POWER_GREEN/blink_counter_enb, loads : 8 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : SPI_BUS_COMMUNICATION/BUS_INTERFACE/master_bus_o.we, loads : 83 Net : SPI_BUS_COMMUNICATION/BUS_INTERFACE/master_bus_o.adr_0, loads : 57 Net : X_ENCODER/MEMROY/REGISTERS_1..REG/n18, loads : 44 Net : x_encoder_rst, loads : 37 Net : y_encoder_rst, loads : 37 Net : SPI_BUS_COMMUNICATION/BUS_INTERFACE/master_bus_o.adr_2, loads : 24 Net : POWER_GREEN/led_counter_21__N_1256, loads : 23 Net : POWER_RED/led_counter_21__N_1154, loads : 23 Net : ENVIRONMENT_WHITE/led_counter_21__N_1460, loads : 23 Net : ENVIRONMENT_GREEN/led_counter_21__N_1562, loads : 23 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 18.518519 -name | | | clk0 [get_nets ClockFPGA_c] | 54.001 MHz| 88.574 MHz| 6 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 239.035 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 2.488 secs -------------------------------------------------------------- Nothing is executed for the "Translate" process map -a "MachXO2" -p LCMXO2-7000HC -t TQFP144 -s 4 -oc Commercial "Project_impl1.ngd" -o "Project_impl1_map.ncd" -pr "Project_impl1.prf" -mp "Project_impl1.mrp" -lpf "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/build/Project_impl1.lpf" -lpf "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v1/fpga/constraints.lpf" -c 0 map: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Process the file: Project_impl1.ngd Picdevice="LCMXO2-7000HC" Pictype="TQFP144" Picspeed=4 Remove unused logic Do not produce over sized NCDs. Part used: LCMXO2-7000HCTQFP144, Performance used: 4. Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Running general design DRC... Removing unused logic... Optimizing... Design Summary: Number of registers: 672 out of 7209 (9%) PFU registers: 672 out of 6864 (10%) PIO registers: 0 out of 345 (0%) Number of SLICEs: 413 out of 3432 (12%) SLICEs as Logic/ROM: 413 out of 3432 (12%) SLICEs as RAM: 0 out of 2574 (0%) SLICEs as Carry: 99 out of 3432 (3%) Number of LUT4s: 803 out of 6864 (12%) Number used as logic LUTs: 605 Number used as distributed RAM: 0 Number used as ripple logic: 198 Number used as shift registers: 0 Number of PIO sites used: 47 + 4(JTAG) out of 115 (44%) Number of block RAMs: 0 out of 26 (0%) Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 2 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 1 Net ClockFPGA_c: 378 loads, 378 rising, 0 falling (Driver: PIO ClockFPGA ) Number of Clock Enables: 58 Net POWER_GREEN/blink_counter_enb: 4 loads, 4 LSLICEs Net p_data_out_7__N_1294: 4 loads, 4 LSLICEs Net GPIO_MANAGEMENT/MEMORY/ClockFPGA_c_enable_26: 5 loads, 5 LSLICEs Net GPIO_MANAGEMENT/MEMORY/ClockFPGA_c_enable_17: 5 loads, 5 LSLICEs Net POWER_RED/blink_counter_enb: 4 loads, 4 LSLICEs Net p_data_out_7__N_1192: 4 loads, 4 LSLICEs Net ENVIRONMENT_WHITE/blink_counter_enb: 4 loads, 4 LSLICEs Net p_data_out_7__N_1498: 4 loads, 4 LSLICEs Net ERROR_LIST/ClockFPGA_c_enable_114: 1 loads, 1 LSLICEs Net ERROR_LIST/ClockFPGA_c_enable_111: 1 loads, 1 LSLICEs Net ERROR_LIST/ClockFPGA_c_enable_129: 1 loads, 1 LSLICEs Net X_ENCODER/ClockFPGA_c_enable_80: 9 loads, 9 LSLICEs Net p_data_out_7__N_857: 4 loads, 4 LSLICEs Net p_data_out_7__N_1396: 4 loads, 4 LSLICEs Net p_data_out_7__N_954: 4 loads, 4 LSLICEs Net p_data_out_7__N_1051: 4 loads, 4 LSLICEs Net ENVIRONMENT_GREEN/blink_counter_enb: 4 loads, 4 LSLICEs Net p_data_out_7__N_1600: 4 loads, 4 LSLICEs Net X_AXIS_MOTOR/ClockFPGA_c_enable_53: 4 loads, 4 LSLICEs Net X_AXIS_MOTOR/ClockFPGA_c_enable_103: 1 loads, 1 LSLICEs Net p_data_out_7__N_824: 4 loads, 4 LSLICEs Net Y_AXIS_MOTOR/ClockFPGA_c_enable_46: 4 loads, 4 LSLICEs Net Y_AXIS_MOTOR/ClockFPGA_c_enable_128: 1 loads, 1 LSLICEs Net p_data_out_7__N_921: 4 loads, 4 LSLICEs Net Y_ENCODER/ClockFPGA_c_enable_95: 9 loads, 9 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_65: 4 loads, 4 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_29: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_58: 3 loads, 3 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_32: 3 loads, 3 LSLICEs Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_8: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_119: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_118: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_122: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_123: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_117: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_109: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_120: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_121: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_98: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_104: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_97: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_101: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_106: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_105: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_96: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_99: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_100: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_108: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_110: 1 loads, 1 LSLICEs Net ClockFPGA_c_enable_113: 1 loads, 1 LSLICEs Net SPI_BUS_COMMUNICATION/BUS_INTERFACE/ClockFPGA_c_enable_127: 6 loads, 6 LSLICEs Net p_data_out_7__N_1090: 4 loads, 4 LSLICEs Net p_data_out_7__N_1018: 4 loads, 4 LSLICEs Net p_data_out_7__N_230: 4 loads, 4 LSLICEs Net ENVIRONMENT_RED/blink_counter_enb: 4 loads, 4 LSLICEs Net CLAW_MAGNET/ClockFPGA_c_enable_54: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/ClockFPGA_c_enable_39: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/ClockFPGA_c_enable_115: 1 loads, 1 LSLICEs Number of LSRs: 45 Net master_bus_i.dat_7__N_21: 4 loads, 4 LSLICEs Net POWER_GREEN/led_counter_21__N_1256: 12 loads, 12 LSLICEs Net n4330: 4 loads, 4 LSLICEs Net x_encoder_rst: 20 loads, 20 LSLICEs Net GPIO_MANAGEMENT/MEMORY/n4350: 5 loads, 5 LSLICEs Net POWER_RED/led_counter_21__N_1154: 12 loads, 12 LSLICEs Net n4351: 4 loads, 4 LSLICEs Net ENVIRONMENT_WHITE/led_counter_21__N_1460: 12 loads, 12 LSLICEs Net n4355: 4 loads, 4 LSLICEs Net y_encoder_rst: 20 loads, 20 LSLICEs Net ERROR_LIST/n8791: 1 loads, 1 LSLICEs Net ERROR_LIST/n5864: 1 loads, 1 LSLICEs Net ERROR_LIST/n8804: 1 loads, 1 LSLICEs Net ERROR_LIST/n5862: 1 loads, 1 LSLICEs Net ERROR_LIST/n8805: 1 loads, 1 LSLICEs Net ERROR_LIST/n5860: 1 loads, 1 LSLICEs Net n4357: 4 loads, 4 LSLICEs Net n4347: 5 loads, 5 LSLICEs Net n4361: 5 loads, 5 LSLICEs Net ENVIRONMENT_GREEN/led_counter_21__N_1562: 12 loads, 12 LSLICEs Net n4356: 4 loads, 4 LSLICEs Net X_AXIS_MOTOR/n1781: 3 loads, 3 LSLICEs Net X_AXIS_MOTOR/n1784: 5 loads, 5 LSLICEs Net n4358: 4 loads, 4 LSLICEs Net n4363: 4 loads, 4 LSLICEs Net Y_AXIS_MOTOR/n1788: 3 loads, 3 LSLICEs Net Y_AXIS_MOTOR/n1791: 5 loads, 5 LSLICEs Net n4359: 4 loads, 4 LSLICEs Net n4364: 4 loads, 4 LSLICEs Net SPI_BUS_COMMUNICATION/p_master_bus_o.adr_9__N_191: 11 loads, 11 LSLICEs Net n8860: 16 loads, 16 LSLICEs Net SPI_BUS_COMMUNICATION/n3018: 1 loads, 1 LSLICEs Net n8865: 13 loads, 13 LSLICEs Net SPI_BUS_COMMUNICATION/n3021: 1 loads, 1 LSLICEs Net n4353: 4 loads, 4 LSLICEs Net n4331: 4 loads, 4 LSLICEs Net n4365: 4 loads, 4 LSLICEs Net FPGA_PIN_INTERFACE/BUFF_ARRAY_10..BUFF/SYNC_INPUT/system_io_i_10_.dat: 1 loads, 1 LSLICEs Net ENVIRONMENT_RED/led_counter_21__N_1358: 12 loads, 12 LSLICEs Net n4354: 4 loads, 4 LSLICEs Net CLAW_MAGNET/PS_1_N_1057_0: 1 loads, 1 LSLICEs Net Z_AXIS_MOTOR/n1795: 3 loads, 3 LSLICEs Net Z_AXIS_MOTOR/n1798: 5 loads, 5 LSLICEs Net Z_AXIS_MOTOR/MEMORY/n4360: 4 loads, 4 LSLICEs Net Z_AXIS_MOTOR/MEMORY/REGISTERS_0..REG/n4366: 4 loads, 4 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net master_bus_o.we: 85 loads Net master_bus_o.adr_0: 59 loads Net n18: 47 loads Net SPI_BUS_COMMUNICATION/BUS_INTERFACE/master_bus_o.adr_2: 24 loads Net master_bus_o.adr_3: 22 loads Net master_bus_o.adr_4: 20 loads Net n8860: 20 loads Net spi0_mosi_sync: 20 loads Net x_encoder_rst: 20 loads Net y_encoder_rst: 20 loads Number of warnings: 0 Number of errors: 0 Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 190 MB Dumping design to file Project_impl1_map.ncd. ncd2vdb "Project_impl1_map.ncd" ".vdbs/Project_impl1_map.vdb" Loading device for application ncd2vdb from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. mpartrce -p "Project_impl1.p2t" -f "Project_impl1.p3t" -tf "Project_impl1.pt" "Project_impl1_map.ncd" "Project_impl1.ncd" ---- MParTrce Tool ---- Removing old design directory at request of -rem command line option to this program. Running par. Please wait . . . Lattice Place and Route Report for Design "Project_impl1_map.ncd" Tue Jun 18 13:33:45 2024 PAR: Place And Route Diamond (64-bit) 3.12.0.240.2. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 Project_impl1_map.ncd Project_impl1.dir/5_1.ncd Project_impl1.prf Preference file: Project_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file Project_impl1_map.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 47+4(JTAG)/336 15% used 47+4(JTAG)/115 44% bonded SLICE 413/3432 12% used GSR 1/1 100% used Number of Signals: 1527 Number of Connections: 3866 Pin Constraint Summary: 47 out of 47 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: ClockFPGA_c (driver: ClockFPGA, clk load #: 378) The following 8 signals are selected to use the secondary clock routing resources: x_encoder_rst (driver: SLICE_586, clk load #: 0, sr load #: 20, ce load #: 0) y_encoder_rst (driver: SLICE_586, clk load #: 0, sr load #: 20, ce load #: 0) n8860 (driver: SLICE_515, clk load #: 0, sr load #: 16, ce load #: 0) n8865 (driver: SLICE_517, clk load #: 0, sr load #: 13, ce load #: 0) POWER_GREEN/led_counter_21__N_1256 (driver: SLICE_184, clk load #: 0, sr load #: 12, ce load #: 0) POWER_RED/led_counter_21__N_1154 (driver: SLICE_193, clk load #: 0, sr load #: 12, ce load #: 0) ENVIRONMENT_WHITE/led_counter_21__N_1460 (driver: SLICE_128, clk load #: 0, sr load #: 12, ce load #: 0) ENVIRONMENT_GREEN/led_counter_21__N_1562 (driver: SLICE_110, clk load #: 0, sr load #: 12, ce load #: 0) Signal rst is selected as Global Set/Reset. Starting Placer Phase 0. .......... Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. .................. Placer score = 242464. Finished Placer Phase 1. REAL time: 6 secs Starting Placer Phase 2. . Placer score = 237426 Finished Placer Phase 2. REAL time: 6 secs ------------------ Clock Report ------------------ Global Clock Resources: CLK_PIN : 1 out of 8 (12%) PLL : 0 out of 2 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: PRIMARY "ClockFPGA_c" from comp "ClockFPGA" on CLK_PIN site "128 (PT18A)", clk load = 378 SECONDARY "x_encoder_rst" from F0 on comp "SLICE_586" on site "R14C20A", clk load = 0, ce load = 0, sr load = 20 SECONDARY "y_encoder_rst" from F1 on comp "SLICE_586" on site "R14C20A", clk load = 0, ce load = 0, sr load = 20 SECONDARY "n8860" from F0 on comp "SLICE_515" on site "R14C20B", clk load = 0, ce load = 0, sr load = 16 SECONDARY "n8865" from F0 on comp "SLICE_517" on site "R14C20D", clk load = 0, ce load = 0, sr load = 13 SECONDARY "POWER_GREEN/led_counter_21__N_1256" from F0 on comp "SLICE_184" on site "R14C18C", clk load = 0, ce load = 0, sr load = 12 SECONDARY "POWER_RED/led_counter_21__N_1154" from F0 on comp "SLICE_193" on site "R14C18D", clk load = 0, ce load = 0, sr load = 12 SECONDARY "ENVIRONMENT_WHITE/led_counter_21__N_1460" from F0 on comp "SLICE_128" on site "R21C20C", clk load = 0, ce load = 0, sr load = 12 SECONDARY "ENVIRONMENT_GREEN/led_counter_21__N_1562" from F0 on comp "SLICE_110" on site "R21C20A", clk load = 0, ce load = 0, sr load = 12 PRIMARY : 1 out of 8 (12%) SECONDARY: 8 out of 8 (100%) Edge Clocks: No edge clock selected. --------------- End of Clock Report --------------- I/O Usage Summary (final): 47 + 4(JTAG) out of 336 (15.2%) PIO sites used. 47 + 4(JTAG) out of 115 (44.3%) bonded PIO sites used. Number of PIO comps: 47; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ | 0 | 15 / 28 ( 53%) | 3.3V | - | | 1 | 29 / 29 (100%) | 3.3V | - | | 2 | 0 / 29 ( 0%) | - | - | | 3 | 0 / 9 ( 0%) | - | - | | 4 | 0 / 10 ( 0%) | - | - | | 5 | 3 / 10 ( 30%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 6 secs Dumping design to file Project_impl1.dir/5_1.ncd. 0 connections routed; 3866 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 7 secs Start NBR router at Tue Jun 18 13:33:52 UTC 2024 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at Tue Jun 18 13:33:53 UTC 2024 Start NBR section for initial routing at Tue Jun 18 13:33:53 UTC 2024 Level 1, iteration 1 0(0.00%) conflict; 2892(74.81%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 7.293ns/0.000ns; real time: 8 secs Level 2, iteration 1 0(0.00%) conflict; 2890(74.75%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 8.117ns/0.000ns; real time: 8 secs Level 3, iteration 1 0(0.00%) conflict; 2886(74.65%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 8.286ns/0.000ns; real time: 8 secs Level 4, iteration 1 168(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 7.952ns/0.000ns; real time: 8 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at Tue Jun 18 13:33:53 UTC 2024 Level 4, iteration 1 99(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.300ns/0.000ns; real time: 9 secs Level 4, iteration 2 63(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.300ns/0.000ns; real time: 9 secs Level 4, iteration 3 25(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.300ns/0.000ns; real time: 9 secs Level 4, iteration 4 13(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.300ns/0.000ns; real time: 9 secs Level 4, iteration 5 4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.051ns/0.000ns; real time: 9 secs Level 4, iteration 6 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.051ns/0.000ns; real time: 9 secs Level 4, iteration 7 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.051ns/0.000ns; real time: 9 secs Start NBR section for setup/hold timing optimization with effort level 3 at Tue Jun 18 13:33:54 UTC 2024 Start NBR section for re-routing at Tue Jun 18 13:33:54 UTC 2024 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.051ns/0.000ns; real time: 9 secs Start NBR section for post-routing at Tue Jun 18 13:33:54 UTC 2024 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack : 8.051ns Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 9 secs Total REAL time: 10 secs Completely routed. End of route. 3866 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file Project_impl1.dir/5_1.ncd. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack> = 8.051 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Worst slack> = 0.304 PAR_SUMMARY::Timing score> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 10 secs Total REAL time to completion: 10 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Exiting par with exit code 0 Exiting mpartrce with exit code 0 trce -f "Project_impl1.pt" -o "Project_impl1.twr" "Project_impl1.ncd" "Project_impl1.prf" trce: version Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application trce from file Project_impl1.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2 Tue Jun 18 13:33:57 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Project_impl1.twr Project_impl1.ncd Project_impl1.prf Design file: Project_impl1.ncd Preference file: Project_impl1.prf Device,speed: LCMXO2-7000HC,4 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 8987 paths, 1 nets, and 3752 connections (97.05% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 Tue Jun 18 13:33:57 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Project_impl1.twr Project_impl1.ncd Project_impl1.prf Design file: Project_impl1.ncd Preference file: Project_impl1.prf Device,speed: LCMXO2-7000HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 8987 paths, 1 nets, and 3752 connections (97.05% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 153 MB Nothing is executed for the "PAR - PARTrace" process tmcheck -par "Project_impl1.par" bitgen -f "Project_impl1.t2b" -w "Project_impl1.ncd" "Project_impl1.prf" BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Loading design for application Bitgen from file Project_impl1.ncd. Design name: TOP_LEVEL NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-7000HC Package: TQFP144 Performance: 4 Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga. Package Status: Final Version 1.39. Performance Hardware Data Status: Final Version 34.4. Running DRC. DRC detected 0 errors and 0 warnings. Reading Preference File from Project_impl1.prf. Preference Summary: +---------------------------------+---------------------------------+ | Preference | Current Setting | +---------------------------------+---------------------------------+ | RamCfg | Reset** | +---------------------------------+---------------------------------+ | MCCLK_FREQ | 2.08** | +---------------------------------+---------------------------------+ | CONFIG_SECURE | OFF** | +---------------------------------+---------------------------------+ | INBUF | ON** | +---------------------------------+---------------------------------+ | JTAG_PORT | ENABLE** | +---------------------------------+---------------------------------+ | SDM_PORT | DISABLE** | +---------------------------------+---------------------------------+ | SLAVE_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MASTER_SPI_PORT | DISABLE** | +---------------------------------+---------------------------------+ | I2C_PORT | DISABLE** | +---------------------------------+---------------------------------+ | MUX_CONFIGURATION_PORTS | DISABLE** | +---------------------------------+---------------------------------+ | CONFIGURATION | CFG** | +---------------------------------+---------------------------------+ | COMPRESS_CONFIG | ON** | +---------------------------------+---------------------------------+ | MY_ASSP | OFF** | +---------------------------------+---------------------------------+ | ONE_TIME_PROGRAM | OFF** | +---------------------------------+---------------------------------+ | ENABLE_TRANSFR | DISABLE** | +---------------------------------+---------------------------------+ | SHAREDEBRINIT | DISABLE** | +---------------------------------+---------------------------------+ | BACKGROUND_RECONFIG | OFF** | +---------------------------------+---------------------------------+ * Default setting. ** The specified setting matches the default setting. Creating bit map... Bitstream Status: Final Version 1.95. Saving bit stream in "Project_impl1.bit". Total CPU Time: 2 secs Total REAL Time: 2 secs Peak Memory Usage: 427 MB RTNETLINK answers: File exists Lattice Diamond Deployment Tool 3.12 Command Line Loading Programmer Device Database... Generating SVF..... Reading Input File: build/Project_impl1.bit Output File: dist/bitstream.svf Generate Single SVF file: Start Device 1 LCMXO2-7000HC:SRAM Erase,Program,Verify Build SVF File Operation: Successful. Lattice Diamond Deployment Tool has exited successfully.