RTNETLINK answers: File exists
synthesis -f "Project_impl1_lattice.synproj"
synthesis: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Tue Jun 18 13:38:21 2024
Command Line: synthesis -f Project_impl1_lattice.synproj
INFO - synthesis: Lattice Synthesis Engine Launched.
Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is TQFP144.
The -d option is LCMXO2-7000HC.
Using package TQFP144.
Using performance grade 4.
##########################################################
### Lattice Family : MachXO2
### Device : LCMXO2-7000HC
### Package : TQFP144
### Speed : 4
##########################################################
INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = TOP_LEVEL.
Target frequency = 54.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p /usr/local/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/build (searchpath added)
-p /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga (searchpath added)
VHDL library = work
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/TOP_LEVEL.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/GOLDI_MODULE_CONFIG.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/ACTUATOR_MASK.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/ERROR_DETECTOR.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/REGISTER_TABLE.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/EMAGNET_SMODULE.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/EMAGNET_SMODULE_2.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/LED_SMODULE.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_DRIVER.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/Divider1MioByX_v1_00.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/StepperControl_v1_00.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/REGISTER_UNIT.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/STREAM_FIFO.vhd
VHDL design file = /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd
NGD file = Project_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
-vh2008
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file /usr/local/diamond/3.12/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
INFO - synthesis: The default VHDL library search path is now "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/build". VHDL-1504
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(39): analyzing package goldi_comm_standard. VHDL-1014
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/libraries/GOLDI_COMM_STANDARD.vhd(255): analyzing package body goldi_comm_standard. VHDL-1013
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/libraries/GOLDI_IO_STANDARD.vhd(32): analyzing package goldi_io_standard. VHDL-1014
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/libraries/GOLDI_DATA_TYPES.vhd(32): analyzing package goldi_data_types. VHDL-1014
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/GOLDI_MODULE_CONFIG.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/GOLDI_MODULE_CONFIG.vhd(38): analyzing package goldi_module_config. VHDL-1014
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd(38): analyzing entity synchronizer. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/SYNCHRONIZER.vhd(54): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(47): analyzing entity sp_converter. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/SP_CONVERTER.vhd(71): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(75): analyzing entity bus_adaptor. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/BUS_ADAPTOR.vhd(96): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(77): analyzing entity goldi_spi_smodule. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/goldi_spi/GOLDI_SPI_SMODULE.vhd(97): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/REGISTER_UNIT.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/REGISTER_UNIT.vhd(63): analyzing entity register_unit. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/REGISTER_UNIT.vhd(87): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd(42): analyzing entity tris_buffer. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/TRIS_BUFFER.vhd(60): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(42): analyzing entity tris_buffer_array. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/TRIS_BUFFER_ARRAY.vhd(63): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd(42): analyzing entity high_debounce. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/HIGH_DEBOUNCE.vhd(61): analyzing architecture bh. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/REGISTER_TABLE.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/REGISTER_TABLE.vhd(82): analyzing entity register_table. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/REGISTER_TABLE.vhd(107): analyzing architecture bh. VHDL-1010
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/REGISTER_TABLE.vhd(196): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/ERROR_DETECTOR.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/ERROR_DETECTOR.vhd(44): analyzing entity error_detector. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/ERROR_DETECTOR.vhd(65): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/ACTUATOR_MASK.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/ACTUATOR_MASK.vhd(44): analyzing entity actuator_mask. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/ACTUATOR_MASK.vhd(58): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd(89): analyzing entity encoder_smodule. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd(113): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd(60): analyzing entity gpio_smodule. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/GPIO_SMODULE.vhd(82): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd(56): analyzing entity rom16xn_fifo. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd(78): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/STREAM_FIFO.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/STREAM_FIFO.vhd(51): analyzing entity stream_fifo. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/STREAM_FIFO.vhd(74): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd(64): analyzing entity spi_t_driver. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/comms/spi/SPI_T_DRIVER.vhd(95): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/StepperControl_v1_00.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/StepperControl_v1_00.vhd(29): analyzing entity steppercontrol_v1_00. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/StepperControl_v1_00.vhd(45): analyzing architecture behavioral. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd(74): analyzing entity tmc2660_smodule. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_SMODULE.vhd(105): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd(71): analyzing entity hbridge_smodule. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/HBRIDGE_SMODULE.vhd(94): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/EMAGNET_SMODULE.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/EMAGNET_SMODULE.vhd(59): analyzing entity emagnet_smodule. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/EMAGNET_SMODULE.vhd(83): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/LED_SMODULE.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/LED_SMODULE.vhd(71): analyzing entity led_smodule. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/LED_SMODULE.vhd(93): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/TOP_LEVEL.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/TOP_LEVEL.vhd(51): analyzing entity top_level. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/TOP_LEVEL.vhd(71): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/EMAGNET_SMODULE_2.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/EMAGNET_SMODULE_2.vhd(60): analyzing entity emagnet_smodule_2. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/EMAGNET_SMODULE_2.vhd(85): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd(44): analyzing entity tmc2660_config_fifo. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_CONFIG_FIFO.vhd(63): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd(41): analyzing entity tmc2660_spi. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_SPI.vhd(67): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_DRIVER.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_DRIVER.vhd(75): analyzing entity tmc2660_driver. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/TMC2660_DRIVER.vhd(105): analyzing architecture rtl. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/Divider1MioByX_v1_00.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/Divider1MioByX_v1_00.vhd(30): analyzing entity divider1miobyx_v1_00. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/actuation/TMC2660/Divider1MioByX_v1_00.vhd(41): analyzing architecture behavioral. VHDL-1010
Analyzing VHDL file /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd. VHDL-1481
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd(38): analyzing entity synchronizer_array. VHDL-1012
INFO - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/io_management/SYNCHRONIZER_ARRAY.vhd(55): analyzing architecture rtl. VHDL-1010
unit TOP_LEVEL is not yet analyzed. VHDL-1485
/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/TOP_LEVEL.vhd(51): executing TOP_LEVEL(RTL)
WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/TOP_LEVEL.vhd(65): replacing existing netlist TOP_LEVEL(RTL). VHDL-1205
Top module name (VHDL): TOP_LEVEL
Last elaborated design is TOP_LEVEL(RTL)
Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Top-level module name = TOP_LEVEL.
@Inferred core reset on ram net :memory
WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/dsp/ENCODER_SMODULE.vhd(197): Register \X_ENCODER/enc_block_37 is stuck at Zero. VDB-5013
INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/sCurrentState' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
000 -> 000001
001 -> 000010
010 -> 000100
011 -> 001000
100 -> 010000
101 -> 100000
INFO - synthesis: Extracted state machine for register '\Y_AXIS_MOTOR/sCurrentState' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
000 -> 000001
001 -> 000010
010 -> 000100
011 -> 001000
100 -> 010000
101 -> 100000
INFO - synthesis: Extracted state machine for register '\CLAW_MAGNET/PS' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
00 -> 0001
01 -> 0010
10 -> 0100
11 -> 1000
INFO - synthesis: Extracted state machine for register '\SPI_BUS_COMMUNICATION/BUS_INTERFACE/ps_mbus' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
000 -> 00001
001 -> 00010
010 -> 00100
011 -> 01000
100 -> 10000
INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
00 -> 0001
01 -> 0010
10 -> 0100
11 -> 1000
INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/SPI_INTERFACE/ps_spi' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
000 -> 00001
001 -> 00010
010 -> 00100
011 -> 01000
100 -> 10000
INFO - synthesis: Extracted state machine for register '\Y_AXIS_MOTOR/CONFIGURATION_FIFO/data_bit_counter' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
00000 -> 00000000000000000000000000000001
00001 -> 00000000000000000000000000000010
00010 -> 00000000000000000000000000000100
00011 -> 00000000000000000000000000001000
00100 -> 00000000000000000000000000010000
00101 -> 00000000000000000000000000100000
00110 -> 00000000000000000000000001000000
00111 -> 00000000000000000000000010000000
01000 -> 00000000000000000000000100000000
01001 -> 00000000000000000000001000000000
01010 -> 00000000000000000000010000000000
01011 -> 00000000000000000000100000000000
01100 -> 00000000000000000001000000000000
01101 -> 00000000000000000010000000000000
01110 -> 00000000000000000100000000000000
01111 -> 00000000000000001000000000000000
10000 -> 00000000000000010000000000000000
10001 -> 00000000000000100000000000000000
10010 -> 00000000000001000000000000000000
10011 -> 00000000000010000000000000000000
10100 -> 00000000000100000000000000000000
10101 -> 00000000001000000000000000000000
10110 -> 00000000010000000000000000000000
10111 -> 00000000100000000000000000000000
11000 -> 00000001000000000000000000000000
11001 -> 00000010000000000000000000000000
11010 -> 00000100000000000000000000000000
11011 -> 00001000000000000000000000000000
11100 -> 00010000000000000000000000000000
11101 -> 00100000000000000000000000000000
11110 -> 01000000000000000000000000000000
11111 -> 10000000000000000000000000000000
INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/StepperControl/sCurrentState' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
000 -> 00001
001 -> 00010
010 -> 00100
011 -> 01000
100 -> 10000
INFO - synthesis: Extracted state machine for register '\Y_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
00 -> 0001
01 -> 0010
10 -> 0100
11 -> 1000
INFO - synthesis: Extracted state machine for register '\Y_AXIS_MOTOR/SPI_INTERFACE/ps_spi' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
000 -> 00001
001 -> 00010
010 -> 00100
011 -> 01000
100 -> 10000
INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/CONFIGURATION_FIFO/data_bit_counter' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
00000 -> 00000000000000000000000000000001
00001 -> 00000000000000000000000000000010
00010 -> 00000000000000000000000000000100
00011 -> 00000000000000000000000000001000
00100 -> 00000000000000000000000000010000
00101 -> 00000000000000000000000000100000
00110 -> 00000000000000000000000001000000
00111 -> 00000000000000000000000010000000
01000 -> 00000000000000000000000100000000
01001 -> 00000000000000000000001000000000
01010 -> 00000000000000000000010000000000
01011 -> 00000000000000000000100000000000
01100 -> 00000000000000000001000000000000
01101 -> 00000000000000000010000000000000
01110 -> 00000000000000000100000000000000
01111 -> 00000000000000001000000000000000
10000 -> 00000000000000010000000000000000
10001 -> 00000000000000100000000000000000
10010 -> 00000000000001000000000000000000
10011 -> 00000000000010000000000000000000
10100 -> 00000000000100000000000000000000
10101 -> 00000000001000000000000000000000
10110 -> 00000000010000000000000000000000
10111 -> 00000000100000000000000000000000
11000 -> 00000001000000000000000000000000
11001 -> 00000010000000000000000000000000
11010 -> 00000100000000000000000000000000
11011 -> 00001000000000000000000000000000
11100 -> 00010000000000000000000000000000
11101 -> 00100000000000000000000000000000
11110 -> 01000000000000000000000000000000
11111 -> 10000000000000000000000000000000
INFO - synthesis: Extracted state machine for register '\Y_AXIS_MOTOR/StepperControl/sCurrentState' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
000 -> 00001
001 -> 00010
010 -> 00100
011 -> 01000
100 -> 10000
INFO - synthesis: Extracted state machine for register '\X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sCurrentState' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
000 -> 00001
001 -> 00010
010 -> 00100
011 -> 01000
100 -> 10000
INFO - synthesis: Extracted state machine for register '\Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sCurrentState' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
000 -> 00001
001 -> 00010
010 -> 00100
011 -> 01000
100 -> 10000
WARNING - synthesis: Bit 0 of Register \SENSOR_REGISTER/sys_bus_o.dat is stuck at Zero
WARNING - synthesis: Bit 0 of Register \ERROR_LIST/MEMORY/REGISTERS[1].REG/sys_bus_o.dat is stuck at Zero
WARNING - synthesis: Bit 1 of Register \ERROR_LIST/MEMORY/REGISTERS[1].REG/sys_bus_o.dat is stuck at Zero
WARNING - synthesis: Bit 2 of Register \ERROR_LIST/MEMORY/REGISTERS[1].REG/sys_bus_o.dat is stuck at Zero
WARNING - synthesis: Bit 19 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 0 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero
WARNING - synthesis: Bit 1 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero
WARNING - synthesis: Bit 2 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero
WARNING - synthesis: Bit 3 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero
WARNING - synthesis: Bit 19 of Register \Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 0 of Register \Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero
WARNING - synthesis: Bit 1 of Register \Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero
WARNING - synthesis: Bit 2 of Register \Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero
WARNING - synthesis: Bit 3 of Register \Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDivisor is stuck at Zero
WARNING - synthesis: Bit 0 of Register \X_AXIS_MOTOR/StepperControl/sMovementState is stuck at Zero
WARNING - synthesis: Bit 0 of Register \Y_AXIS_MOTOR/StepperControl/sMovementState is stuck at Zero
WARNING - synthesis: Bit 18 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 18 of Register \Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 17 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 17 of Register \Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 16 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 16 of Register \Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 15 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 15 of Register \Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 14 of Register \X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
WARNING - synthesis: Bit 14 of Register \Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/sDividend is stuck at Zero
######## Pruned 1 high address bits on RAM Instance : \X_AXIS_MOTOR/STREAM_FIFO/clk_write_port_12 on net : \X_AXIS_MOTOR/STREAM_FIFO/memory
######## Pruned 1 high address bits on RAM Instance : \X_AXIS_MOTOR/STREAM_FIFO/rd_pointer_2__N_869_2__I_0 on net : \X_AXIS_MOTOR/STREAM_FIFO/memory
######## Pruned 1 high address bits on RAM Instance : \Y_AXIS_MOTOR/STREAM_FIFO/rd_pointer_2__N_869_2__I_0 on net : \Y_AXIS_MOTOR/STREAM_FIFO/memory
######## Pruned 1 high address bits on RAM Instance : \Y_AXIS_MOTOR/STREAM_FIFO/clk_write_port_12 on net : \Y_AXIS_MOTOR/STREAM_FIFO/memory
Core reset RAM implemented for net n6452.
Core reset RAM implemented for net n6453.
######## Found 2 RTL RAMs in the design.
######## Mapping RTL RAM n6452 to 6 Distributed blocks in PSEUDO_DUAL_PORT Mode
######## Mapping RTL RAM n6453 to 6 Distributed blocks in PSEUDO_DUAL_PORT Mode
WARNING - synthesis: Register creset_2789 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2780 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2776 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2772 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2768 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2764 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2760 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2756 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2849 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2845 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2841 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2837 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2833 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2829 is stuck at Zero. VDB-5013
WARNING - synthesis: Register creset_2825 is stuck at Zero. VDB-5013
WARNING - synthesis: Skipping pad insertion on IO_DATA[41] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[40] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[39] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[38] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[37] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[36] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[35] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[34] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[33] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[32] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[31] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[30] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[29] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[28] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[27] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[26] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[25] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[24] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[23] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[22] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[21] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[20] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[19] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[18] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[17] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[16] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[15] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[14] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[13] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[12] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[11] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[10] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[9] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[8] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[7] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[6] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[5] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[4] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[3] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[2] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[1] due to black_box_pad_pin attribute.
WARNING - synthesis: Skipping pad insertion on IO_DATA[0] due to black_box_pad_pin attribute.
WARNING - synthesis: /builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/src/common/memory/ROM16XN_FIFO.vhd(273): Register \Y_AXIS_MOTOR/CONFIGURATION_FIFO/data_bit_counter_FSM_i24 is stuck at Zero. VDB-5013
Optimized async. reset : rst on data cone feeding flop :
\Y_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i1
\Y_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i3
\Y_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i4
Optimized async. reset : rst on data cone feeding flop :
\X_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i1
\X_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i3
\X_AXIS_MOTOR/CONFIGURATION_FIFO/ps_fifo_FSM_i4
GSR instance connected to net n10089.
Applying 54.000000 MHz constraint to all clocks
WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in TOP_LEVEL_drc.log.
Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library '/usr/local/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library '/usr/local/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library '/usr/local/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Running DRC...
WARNING - synthesis: logical net 'port_in_async_13_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_14_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_16_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_17_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_18_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_19_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_20_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_22_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_23_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_25_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_26_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_27_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_28_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_29_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_31_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_32_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_33_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_34_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_35_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_36_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_37_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_38_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_39_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_40_.dat' has no load.
WARNING - synthesis: logical net 'port_in_async_41_.dat' has no load.
WARNING - synthesis: DRC complete with 25 warnings.
Design Results:
3498 blocks expanded
completed the first expansion
All blocks are expanded and NGD expansion is successful.
Writing NGD file Project_impl1.ngd.
################### Begin Area Report (TOP_LEVEL)######################
Number of register bits => 1582 of 7209 (21 % )
BB => 42
CCU2D => 275
DPR16X4C => 12
FD1P3AX => 480
FD1P3AY => 16
FD1P3DX => 60
FD1P3IX => 345
FD1P3JX => 21
FD1S3AX => 118
FD1S3AY => 16
FD1S3DX => 104
FD1S3IX => 413
FD1S3JX => 9
GSR => 1
IB => 5
L6MUX21 => 11
LUT4 => 1473
OB => 1
PFUMX => 77
ROM16X1A => 16
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 1
Net : ClockFPGA_c, loads : 1594
Clock Enable Nets
Number of Clock Enables: 213
Top 10 highest fanout Clock Enables:
Net : X_AXIS_MOTOR/SPI_INTERFACE/ps_spi_2_N_997_0, loads : 28
Net : Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_365, loads : 27
Net : Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_431, loads : 24
Net : X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_332, loads : 24
Net : Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_574, loads : 24
Net : X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_284, loads : 24
Net : X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_462, loads : 23
Net : Y_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_52, loads : 23
Net : Y_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_387, loads : 20
Net : X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_489, loads : 20
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : SPI_BUS_COMMUNICATION/BUS_INTERFACE/master_bus_o.we, loads : 110
Net : Y_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_820, loads : 57
Net : X_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_820, loads : 56
Net : SENSOR_REGISTER/n18, loads : 54
Net : RESET_SYNC/n20836, loads : 52
Net : X_AXIS_MOTOR/n20129, loads : 47
Net : RESET_SYNC/ClockFPGA_c_enable_520, loads : 45
Net : RESET_SYNC/n20046, loads : 44
Net : Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_540, loads : 40
Net : X_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_406, loads : 40
################### End Clock Report ##################
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 18.518519 -name | | |
clk0 [get_nets ClockFPGA_c] | 54.001 MHz| 51.515 MHz| 14 *
| | |
--------------------------------------------------------------------------------
1 constraints not met.
Peak Memory Usage: 262.879 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 6.029 secs
--------------------------------------------------------------
Nothing is executed for the "Translate" process
map -a "MachXO2" -p LCMXO2-7000HC -t TQFP144 -s 4 -oc Commercial "Project_impl1.ngd" -o "Project_impl1_map.ncd" -pr "Project_impl1.prf" -mp "Project_impl1.mrp" -lpf "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/build/Project_impl1.lpf" -lpf "/builds/FakIA/fachgebiet-iks/goldi/goldi2/goldi2/hardware/boards/axis_portal_v2/fpga/constraints.lpf" -c 0
map: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Process the file: Project_impl1.ngd
Picdevice="LCMXO2-7000HC"
Pictype="TQFP144"
Picspeed=4
Remove unused logic
Do not produce over sized NCDs.
Part used: LCMXO2-7000HCTQFP144, Performance used: 4.
Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Running general design DRC...
Removing unused logic...
Optimizing...
Design Summary:
Number of registers: 1582 out of 7209 (22%)
PFU registers: 1582 out of 6864 (23%)
PIO registers: 0 out of 345 (0%)
Number of SLICEs: 1091 out of 3432 (32%)
SLICEs as Logic/ROM: 1055 out of 3432 (31%)
SLICEs as RAM: 36 out of 2574 (1%)
SLICEs as Carry: 275 out of 3432 (8%)
Number of LUT4s: 2116 out of 6864 (31%)
Number used as logic LUTs: 1494
Number used as distributed RAM: 72
Number used as ripple logic: 550
Number used as shift registers: 0
Number of PIO sites used: 48 + 4(JTAG) out of 115 (45%)
Number of block RAMs: 0 out of 26 (0%)
Number of GSRs: 1 out of 1 (100%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 2 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
Number of clocks: 1
Net ClockFPGA_c: 1007 loads, 1007 rising, 0 falling (Driver: PIO ClockFPGA )
Number of Clock Enables: 213
Net ClockFPGA_c_enable_4: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_5: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_6: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_9: 1 loads, 1 LSLICEs
Net wr_pointer_2__N_884: 3 loads, 3 LSLICEs
Net ClockFPGA_c_enable_257: 2 loads, 2 LSLICEs
Net ClockFPGA_c_enable_40: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_54: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_57: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_58: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_69: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_102: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_108: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_117: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_125: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_342: 3 loads, 3 LSLICEs
Net ClockFPGA_c_enable_285: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_307: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_94: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_286: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_287: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_288: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_289: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_140: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_290: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_291: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_292: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_293: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_294: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_295: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_296: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_297: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_298: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_299: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_300: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_301: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_302: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_303: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_304: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_305: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_306: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_166: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_168: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_172: 3 loads, 3 LSLICEs
Net ClockFPGA_c_enable_204: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_205: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_206: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_203: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_202: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_201: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_200: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_199: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_198: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_197: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_196: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_195: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_194: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_193: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_192: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_191: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_190: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_189: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_188: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_187: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_186: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_185: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_184: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_55: 1 loads, 1 LSLICEs
Net GPIO_MANAGEMENT/MEMORY/ClockFPGA_c_enable_183: 5 loads, 5 LSLICEs
Net GPIO_MANAGEMENT/MEMORY/ClockFPGA_c_enable_604: 5 loads, 5 LSLICEs
Net ClockFPGA_c_enable_96: 1 loads, 1 LSLICEs
Net rst: 24 loads, 24 LSLICEs
Net ClockFPGA_c_enable_509: 8 loads, 8 LSLICEs
Net ClockFPGA_c_enable_136: 8 loads, 8 LSLICEs
Net ClockFPGA_c_enable_106: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_110: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_555: 8 loads, 8 LSLICEs
Net ClockFPGA_c_enable_97: 1 loads, 1 LSLICEs
Net ENVIRONMENT_GREEN/blink_counter_enb: 4 loads, 4 LSLICEs
Net p_data_out_7__N_2725: 4 loads, 4 LSLICEs
Net ENVIRONMENT_RED/blink_counter_enb: 4 loads, 4 LSLICEs
Net p_data_out_7__N_2521: 4 loads, 4 LSLICEs
Net ERROR_LIST/Z_STEPPER_ON/shift_reg_4__N_290: 2 loads, 2 LSLICEs
Net ERROR_LIST/Y_STEPPER_ON/shift_reg_4__N_290: 2 loads, 2 LSLICEs
Net ERROR_LIST/X_STEPPER_ON/shift_reg_4__N_290: 2 loads, 2 LSLICEs
Net ps_spi_2_N_997_0: 12 loads, 12 LSLICEs
Net ClockFPGA_c_enable_339: 2 loads, 2 LSLICEs
Net CLAW_MAGNET/ClockFPGA_c_enable_505: 1 loads, 1 LSLICEs
Net p_data_out_7__N_2215: 4 loads, 4 LSLICEs
Net ClockFPGA_c_enable_266: 2 loads, 2 LSLICEs
Net Y_AXIS_MOTOR/spi_r_tvalid: 12 loads, 12 LSLICEs
Net Y_AXIS_MOTOR/ClockFPGA_c_enable_556: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/ClockFPGA_c_enable_408: 2 loads, 2 LSLICEs
Net Y_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_387: 11 loads, 11 LSLICEs
Net Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_141: 8 loads, 8 LSLICEs
Net Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_574: 19 loads, 19 LSLICEs
Net Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_540: 10 loads, 10 LSLICEs
Net ClockFPGA_c_enable_365: 12 loads, 12 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_150: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_149: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_148: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_147: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_142: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_139: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_138: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_137: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_431: 13 loads, 13 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_129: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_143: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_144: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_145: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_146: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_151: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_152: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_153: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_155: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_156: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_157: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_158: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_159: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_161: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_162: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_165: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_439: 2 loads, 2 LSLICEs
Net p_data_out_7__N_1982: 4 loads, 4 LSLICEs
Net p_data_out_7__N_1949: 4 loads, 4 LSLICEs
Net Y_AXIS_MOTOR/MEMORY/REGISTERS_3..REG/p_data_out_7__N_1916: 4 loads, 4 LSLICEs
Net p_data_out_7__N_1710: 4 loads, 4 LSLICEs
Net p_data_out_7__N_2079: 4 loads, 4 LSLICEs
Net p_data_out_7__N_1883: 4 loads, 4 LSLICEs
Net p_data_out_7__N_1850: 4 loads, 4 LSLICEs
Net p_data_out_7__N_1817: 4 loads, 4 LSLICEs
Net Y_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_2: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_52: 12 loads, 12 LSLICEs
Net ClockFPGA_c_enable_368: 2 loads, 2 LSLICEs
Net Y_ENCODER/ClockFPGA_c_enable_590: 9 loads, 9 LSLICEs
Net X_ENCODER/ClockFPGA_c_enable_255: 9 loads, 9 LSLICEs
Net SYSTEM_CONFIG_REG/p_data_out_7__N_231: 4 loads, 4 LSLICEs
Net p_data_out_7__N_1611: 4 loads, 4 LSLICEs
Net p_data_out_7__N_2623: 4 loads, 4 LSLICEs
Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_218: 3 loads, 3 LSLICEs
Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_127: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_229: 3 loads, 3 LSLICEs
Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_597: 4 loads, 4 LSLICEs
Net SPI_BUS_COMMUNICATION/ClockFPGA_c_enable_208: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_629: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_631: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_507: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_630: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_634: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_635: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/DATA_SP_CONVERTER/ClockFPGA_c_enable_633: 1 loads, 1 LSLICEs
Net ClockFPGA_c_enable_632: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_627: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_628: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_626: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_623: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_622: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_621: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_624: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_618: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_619: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_620: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_625: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/CONFIGURATION_SP_CONVERTER/ClockFPGA_c_enable_606: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/BUS_INTERFACE/ClockFPGA_c_enable_639: 5 loads, 5 LSLICEs
Net ENVIRONMENT_WHITE/blink_counter_enb: 4 loads, 4 LSLICEs
Net p_data_out_7__N_2046: 5 loads, 5 LSLICEs
Net p_data_out_7__N_1545: 4 loads, 4 LSLICEs
Net p_data_out_7__N_1677: 4 loads, 4 LSLICEs
Net p_data_out_7__N_2419: 4 loads, 4 LSLICEs
Net p_data_out_7__N_1644: 4 loads, 4 LSLICEs
Net p_data_out_7__N_2317: 4 loads, 4 LSLICEs
Net Z_AXIS_MOTOR/ClockFPGA_c_enable_240: 4 loads, 4 LSLICEs
Net Z_AXIS_MOTOR/ClockFPGA_c_enable_605: 1 loads, 1 LSLICEs
Net POWER_RED/blink_counter_enb: 4 loads, 4 LSLICEs
Net X_AXIS_MOTOR/spi_r_tvalid: 12 loads, 12 LSLICEs
Net X_AXIS_MOTOR/ClockFPGA_c_enable_463: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/ClockFPGA_c_enable_309: 2 loads, 2 LSLICEs
Net X_AXIS_MOTOR/StepperControl/ClockFPGA_c_enable_406: 11 loads, 11 LSLICEs
Net X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_284: 19 loads, 19 LSLICEs
Net X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_118: 8 loads, 8 LSLICEs
Net X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_489: 10 loads, 10 LSLICEs
Net X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_504: 8 loads, 8 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_332: 13 loads, 13 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_154: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_518: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_517: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_515: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_514: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_513: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_512: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_511: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_510: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_615: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_617: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_616: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_614: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_613: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_612: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_611: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_519: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_521: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_522: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_575: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_610: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_609: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_608: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/ClockFPGA_c_enable_607: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/MEMORY/p_data_out_7__N_1578: 4 loads, 4 LSLICEs
Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_462: 12 loads, 12 LSLICEs
Net X_AXIS_MOTOR/CONFIGURATION_FIFO/ClockFPGA_c_enable_92: 1 loads, 1 LSLICEs
Net POWER_GREEN/blink_counter_enb: 4 loads, 4 LSLICEs
Number of LSRs: 83
Net n20046: 29 loads, 29 LSLICEs
Net n20129: 28 loads, 28 LSLICEs
Net n10908: 7 loads, 7 LSLICEs
Net n2865: 1 loads, 1 LSLICEs
Net n10764: 3 loads, 3 LSLICEs
Net master_bus_i.dat_7__N_22: 4 loads, 4 LSLICEs
Net GPIO_MANAGEMENT/MEMORY/n10743: 5 loads, 5 LSLICEs
Net sCounter1us_5__N_1172_adj_2979: 11 loads, 11 LSLICEs
Net n12159: 8 loads, 8 LSLICEs
Net p_tdword_tready_N_1108: 1 loads, 1 LSLICEs
Net n3126: 1 loads, 1 LSLICEs
Net n12058: 8 loads, 8 LSLICEs
Net sCounter1us_5__N_1172: 11 loads, 11 LSLICEs
Net x_encoder_ref: 27 loads, 27 LSLICEs
Net y_encoder_ref: 29 loads, 29 LSLICEs
Net ENVIRONMENT_GREEN/led_counter_21__N_2687: 12 loads, 12 LSLICEs
Net n20010: 4 loads, 4 LSLICEs
Net ENVIRONMENT_RED/led_counter_21__N_2483: 12 loads, 12 LSLICEs
Net n20012: 4 loads, 4 LSLICEs
Net ERROR_LIST/Z_STEPPER_ON/n10779: 8 loads, 8 LSLICEs
Net ERROR_LIST/Y_STEPPER_ON/n10776: 8 loads, 8 LSLICEs
Net ERROR_LIST/X_STEPPER_ON/n10770: 8 loads, 8 LSLICEs
Net n20030: 3 loads, 3 LSLICEs
Net n20027: 5 loads, 5 LSLICEs
Net miso_buffer_i_23__N_1084: 1 loads, 1 LSLICEs
Net CLAW_MAGNET/PS_1_N_2120_0: 1 loads, 1 LSLICEs
Net CLAW_MAGNET/n10745: 16 loads, 16 LSLICEs
Net n10755: 4 loads, 4 LSLICEs
Net Y_AXIS_MOTOR/sStopMovement: 5 loads, 5 LSLICEs
Net Y_AXIS_MOTOR/sCurrentState_2_N_1748_1: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/StepperControl/n3739: 4 loads, 4 LSLICEs
Net n16277: 7 loads, 7 LSLICEs
Net n16284: 3 loads, 3 LSLICEs
Net Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/n6157: 16 loads, 16 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/n20016: 3 loads, 3 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/n10757: 1 loads, 1 LSLICEs
Net miso_buffer_i_23__N_1084_adj_2975: 1 loads, 1 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/n5903: 4 loads, 4 LSLICEs
Net Y_AXIS_MOTOR/SPI_INTERFACE/n3736: 3 loads, 3 LSLICEs
Net n20000: 4 loads, 4 LSLICEs
Net n20001: 4 loads, 4 LSLICEs
Net Y_AXIS_MOTOR/MEMORY/REGISTERS_3..REG/n20002: 4 loads, 4 LSLICEs
Net n20014: 4 loads, 4 LSLICEs
Net n19999: 4 loads, 4 LSLICEs
Net n20004: 4 loads, 4 LSLICEs
Net n20005: 4 loads, 4 LSLICEs
Net n10782: 4 loads, 4 LSLICEs
Net Y_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_819: 18 loads, 18 LSLICEs
Net Y_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_818: 24 loads, 24 LSLICEs
Net Y_AXIS_MOTOR/CONFIGURATION_FIFO/n3718: 4 loads, 4 LSLICEs
Net n10748: 4 loads, 4 LSLICEs
Net n20003: 4 loads, 4 LSLICEs
Net SPI_BUS_COMMUNICATION/n20105: 16 loads, 16 LSLICEs
Net SPI_BUS_COMMUNICATION/n8038: 1 loads, 1 LSLICEs
Net n20115: 13 loads, 13 LSLICEs
Net SPI_BUS_COMMUNICATION/n8041: 1 loads, 1 LSLICEs
Net SPI_BUS_COMMUNICATION/p_master_bus_o.adr_9__N_192: 10 loads, 10 LSLICEs
Net ENVIRONMENT_WHITE/led_counter_21__N_2585: 12 loads, 12 LSLICEs
Net n10761: 4 loads, 4 LSLICEs
Net n10741: 4 loads, 4 LSLICEs
Net n19998: 4 loads, 4 LSLICEs
Net n20013: 4 loads, 4 LSLICEs
Net n20009: 4 loads, 4 LSLICEs
Net n20015: 4 loads, 4 LSLICEs
Net Z_AXIS_MOTOR/n3612: 5 loads, 5 LSLICEs
Net Z_AXIS_MOTOR/n3609: 3 loads, 3 LSLICEs
Net n10759: 4 loads, 4 LSLICEs
Net n10781: 4 loads, 4 LSLICEs
Net POWER_RED/led_counter_21__N_2279: 12 loads, 12 LSLICEs
Net X_AXIS_MOTOR/sCurrentState_2_N_731_1: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/p_tdword_tready_N_1108: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/sStopMovement: 5 loads, 5 LSLICEs
Net X_AXIS_MOTOR/StepperControl/n3700: 4 loads, 4 LSLICEs
Net X_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/n6120: 16 loads, 16 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/n5901: 4 loads, 4 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/n3697: 3 loads, 3 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/n20022: 3 loads, 3 LSLICEs
Net X_AXIS_MOTOR/SPI_INTERFACE/n10753: 1 loads, 1 LSLICEs
Net X_AXIS_MOTOR/MEMORY/n20008: 4 loads, 4 LSLICEs
Net X_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_819: 18 loads, 18 LSLICEs
Net X_AXIS_MOTOR/CONFIGURATION_FIFO/n3679: 4 loads, 4 LSLICEs
Net X_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_818: 24 loads, 24 LSLICEs
Net POWER_GREEN/led_counter_21__N_2381: 12 loads, 12 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net master_bus_o.we: 112 loads
Net p_cword_tdata_23__N_820_adj_2940: 59 loads
Net p_cword_tdata_23__N_820: 58 loads
Net n18: 55 loads
Net n20836: 53 loads
Net rd_pointer_2_N_869_2: 48 loads
Net rd_pointer_2_N_869_2_adj_2947: 48 loads
Net rst: 46 loads
Net X_AXIS_MOTOR/p_tdword_tready_N_1108: 36 loads
Net p_tdword_tready_N_1108: 34 loads
Number of warnings: 0
Number of errors: 0
Total CPU Time: 1 secs
Total REAL Time: 0 secs
Peak Memory Usage: 201 MB
Dumping design to file Project_impl1_map.ncd.
ncd2vdb "Project_impl1_map.ncd" ".vdbs/Project_impl1_map.vdb"
Loading device for application ncd2vdb from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga.
mpartrce -p "Project_impl1.p2t" -f "Project_impl1.p3t" -tf "Project_impl1.pt" "Project_impl1_map.ncd" "Project_impl1.ncd"
---- MParTrce Tool ----
Removing old design directory at request of -rem command line option to this program.
Running par. Please wait . . .
Lattice Place and Route Report for Design "Project_impl1_map.ncd"
Tue Jun 18 13:38:29 2024
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 Project_impl1_map.ncd Project_impl1.dir/5_1.ncd Project_impl1.prf
Preference file: Project_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file Project_impl1_map.ncd.
Design name: TOP_LEVEL
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-7000HC
Package: TQFP144
Performance: 4
Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 48+4(JTAG)/336 15% used
48+4(JTAG)/115 45% bonded
SLICE 1091/3432 31% used
GSR 1/1 100% used
Number of Signals: 3850
Number of Connections: 10187
Pin Constraint Summary:
48 out of 48 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
ClockFPGA_c (driver: ClockFPGA, clk load #: 1007)
The following 8 signals are selected to use the secondary clock routing resources:
n20046 (driver: SLICE_962, clk load #: 0, sr load #: 29, ce load #: 0)
y_encoder_ref (driver: SLICE_1496, clk load #: 0, sr load #: 29, ce load #: 0)
n20129 (driver: X_AXIS_MOTOR/SLICE_1476, clk load #: 0, sr load #: 28, ce load #: 0)
x_encoder_ref (driver: SLICE_727, clk load #: 0, sr load #: 27, ce load #: 0)
rst (driver: SLICE_1325, clk load #: 0, sr load #: 0, ce load #: 24)
Y_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_818 (driver: Y_AXIS_MOTOR/CONFIGURATION_FIFO/SLICE_975, clk load #: 0, sr load #: 24, ce load #: 0)
X_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_818 (driver: X_AXIS_MOTOR/SLICE_1511, clk load #: 0, sr load #: 24, ce load #: 0)
Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_574 (driver: Y_AXIS_MOTOR/SLICE_1536, clk load #: 0, sr load #: 0, ce load #: 19)
Signal rst is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0. REAL time: 3 secs
Starting Placer Phase 1.
.....................
Placer score = 679367.
Finished Placer Phase 1. REAL time: 9 secs
Starting Placer Phase 2.
.
Placer score = 667927
Finished Placer Phase 2. REAL time: 9 secs
------------------ Clock Report ------------------
Global Clock Resources:
CLK_PIN : 1 out of 8 (12%)
PLL : 0 out of 2 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY "ClockFPGA_c" from comp "ClockFPGA" on CLK_PIN site "128 (PT18A)", clk load = 1007
SECONDARY "n20046" from F1 on comp "SLICE_962" on site "R21C20B", clk load = 0, ce load = 0, sr load = 29
SECONDARY "y_encoder_ref" from F0 on comp "SLICE_1496" on site "R21C20C", clk load = 0, ce load = 0, sr load = 29
SECONDARY "n20129" from F0 on comp "X_AXIS_MOTOR/SLICE_1476" on site "R14C18A", clk load = 0, ce load = 0, sr load = 28
SECONDARY "x_encoder_ref" from F1 on comp "SLICE_727" on site "R21C20A", clk load = 0, ce load = 0, sr load = 27
SECONDARY "rst" from Q1 on comp "SLICE_1325" on site "R14C18B", clk load = 0, ce load = 24, sr load = 0
SECONDARY "Y_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_818" from F1 on comp "Y_AXIS_MOTOR/CONFIGURATION_FIFO/SLICE_975" on site "R14C20B", clk load = 0, ce load = 0, sr load = 24
SECONDARY "X_AXIS_MOTOR/CONFIGURATION_FIFO/p_cword_tdata_23__N_818" from F1 on comp "X_AXIS_MOTOR/SLICE_1511" on site "R14C20C", clk load = 0, ce load = 0, sr load = 24
SECONDARY "Y_AXIS_MOTOR/StepperControl/Divider1MioByX_inst/ClockFPGA_c_enable_574" from F0 on comp "Y_AXIS_MOTOR/SLICE_1536" on site "R14C20D", clk load = 0, ce load = 19, sr load = 0
PRIMARY : 1 out of 8 (12%)
SECONDARY: 8 out of 8 (100%)
Edge Clocks:
No edge clock selected.
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
48 + 4(JTAG) out of 336 (15.5%) PIO sites used.
48 + 4(JTAG) out of 115 (45.2%) bonded PIO sites used.
Number of PIO comps: 48; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 10 / 28 ( 35%) | 3.3V | - |
| 1 | 26 / 29 ( 89%) | 3.3V | - |
| 2 | 1 / 29 ( 3%) | 3.3V | - |
| 3 | 3 / 9 ( 33%) | 3.3V | - |
| 4 | 4 / 10 ( 40%) | 3.3V | - |
| 5 | 4 / 10 ( 40%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 9 secs
Dumping design to file Project_impl1.dir/5_1.ncd.
0 connections routed; 10187 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 12 secs
Start NBR router at Tue Jun 18 13:38:41 UTC 2024
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at Tue Jun 18 13:38:41 UTC 2024
Start NBR section for initial routing at Tue Jun 18 13:38:41 UTC 2024
Level 1, iteration 1
4(0.00%) conflicts; 7655(75.14%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.578ns/0.000ns; real time: 12 secs
Level 2, iteration 1
0(0.00%) conflict; 7656(75.15%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.426ns/0.000ns; real time: 13 secs
Level 3, iteration 1
6(0.00%) conflicts; 7402(72.66%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.454ns/0.000ns; real time: 13 secs
Level 4, iteration 1
390(0.10%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 14 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 19 (1.90%)
Start NBR section for normal routing at Tue Jun 18 13:38:43 UTC 2024
Level 1, iteration 1
0(0.00%) conflict; 532(5.22%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 14 secs
Level 2, iteration 1
0(0.00%) conflict; 532(5.22%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 14 secs
Level 3, iteration 1
1(0.00%) conflict; 531(5.21%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 14 secs
Level 4, iteration 1
249(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 15 secs
Level 4, iteration 2
137(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 15 secs
Level 4, iteration 3
91(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 15 secs
Level 4, iteration 4
46(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Level 4, iteration 5
29(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Level 4, iteration 6
13(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Level 4, iteration 7
8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Level 4, iteration 8
6(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Level 4, iteration 9
8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Level 4, iteration 10
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Level 4, iteration 11
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Level 4, iteration 12
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Level 4, iteration 13
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Level 4, iteration 14
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 16 secs
Start NBR section for setup/hold timing optimization with effort level 3 at Tue Jun 18 13:38:45 UTC 2024
Start NBR section for re-routing at Tue Jun 18 13:38:46 UTC 2024
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.439ns/0.000ns; real time: 17 secs
Start NBR section for post-routing at Tue Jun 18 13:38:46 UTC 2024
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 1.439ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 18 secs
Total REAL time: 18 secs
Completely routed.
End of route. 10187 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file Project_impl1.dir/5_1.ncd.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 1.439
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.220
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 18 secs
Total REAL time to completion: 19 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Exiting par with exit code 0
Exiting mpartrce with exit code 0
trce -f "Project_impl1.pt" -o "Project_impl1.twr" "Project_impl1.ncd" "Project_impl1.prf"
trce: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application trce from file Project_impl1.ncd.
Design name: TOP_LEVEL
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-7000HC
Package: TQFP144
Performance: 4
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Tue Jun 18 13:38:51 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Project_impl1.twr Project_impl1.ncd Project_impl1.prf
Design file: Project_impl1.ncd
Preference file: Project_impl1.prf
Device,speed: LCMXO2-7000HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 55991 paths, 1 nets, and 10101 connections (99.16% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Tue Jun 18 13:38:51 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Project_impl1.twr Project_impl1.ncd Project_impl1.prf
Design file: Project_impl1.ncd
Preference file: Project_impl1.prf
Device,speed: LCMXO2-7000HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 55991 paths, 1 nets, and 10101 connections (99.16% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 166 MB
Nothing is executed for the "PAR - PARTrace" process
tmcheck -par "Project_impl1.par"
bitgen -f "Project_impl1.t2b" -w "Project_impl1.ncd" "Project_impl1.prf"
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application Bitgen from file Project_impl1.ncd.
Design name: TOP_LEVEL
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-7000HC
Package: TQFP144
Performance: 4
Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from Project_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "Project_impl1.bit".
Total CPU Time: 3 secs
Total REAL Time: 3 secs
Peak Memory Usage: 433 MB
RTNETLINK answers: File exists
Lattice Diamond Deployment Tool 3.12 Command Line
Loading Programmer Device Database...
Generating SVF.....
Reading Input File: build/Project_impl1.bit
Output File: dist/bitstream.svf
Generate Single SVF file: Start
Device 1 LCMXO2-7000HC:SRAM Erase,Program,Verify
Build SVF File Operation: Successful.
Lattice Diamond Deployment Tool has exited successfully.